A MCU implementation based PODES-M0O
☆19Jan 31, 2020Updated 6 years ago
Alternatives and similar repositories for AMY_MCU
Users that are interested in AMY_MCU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Jan 31, 2020Updated 6 years ago
- powerpc processor prototype and an example of semiconductor startup biz plan☆14Feb 2, 2019Updated 7 years ago
- ☆18Apr 5, 2015Updated 11 years ago
- verilog/FPGA hardware description for very simple GPU☆16Apr 9, 2019Updated 7 years ago
- 一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU☆11Oct 8, 2019Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆38Aug 12, 2015Updated 10 years ago
- ☆10Aug 12, 2021Updated 4 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- ☆23Dec 7, 2019Updated 6 years ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆24Jun 27, 2023Updated 2 years ago
- Devotes to open source FPGA☆28May 9, 2020Updated 6 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 10 years ago
- commit rtl and build cosim env☆15Feb 15, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A custom 16-bit computer☆12Oct 17, 2018Updated 7 years ago
- 适用于FPGA——利用串口通信接收幅度频率信息数据帧，控制DA输出相应正弦信号☆10Jul 10, 2019Updated 6 years ago
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 9 years ago
- 基于Verilog实现的串口发送程序，带奇偶校验位。☆12Aug 23, 2019Updated 6 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 9 years ago
- SPI core☆12Jul 17, 2014Updated 11 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆24Aug 11, 2020Updated 5 years ago
- Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.☆12Jan 15, 2022Updated 4 years ago
- Implementation of the PCIe physical layer☆63Jul 11, 2025Updated 11 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Jan 6, 2020Updated 6 years ago
- AMBA bus generator including AXI, AHB, and APB☆123Jul 29, 2021Updated 4 years ago
- ☆13May 21, 2019Updated 7 years ago
- measures to assess frequency-weighted instantaneous energy☆17Apr 4, 2022Updated 4 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆14Nov 1, 2018Updated 7 years ago
- 包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）☆25Nov 7, 2022Updated 3 years ago
- RTL Verilog library for various DSP modules☆98Feb 17, 2022Updated 4 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 8 years ago
- Hardware Accelerated MWPM decoder for Quantum Error Correction☆22Mar 23, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A simple DDR3 memory controller☆65Jan 9, 2023Updated 3 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- The biologically plausible self backpropagation on SNNs and ANNs☆13Aug 27, 2021Updated 4 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated 2 years ago
- ☆10Sep 7, 2023Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 11 years ago