sunyata000 / AMY_MCU
A MCU implementation based PODES-M0O
☆18Updated 5 years ago
Alternatives and similar repositories for AMY_MCU:
Users that are interested in AMY_MCU are comparing it to the libraries listed below
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- ☆40Updated 2 years ago
- ☆25Updated 4 years ago
- commit rtl and build cosim env☆14Updated last year
- ☆9Updated 4 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- ☆29Updated 5 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆17Updated 6 years ago
- ☆16Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- The memory model was leveraged from micron.☆22Updated 6 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- ☆16Updated 2 years ago
- A Verilog implementation of a processor cache.☆24Updated 7 years ago
- ☆36Updated 6 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- Implementation of the PCIe physical layer☆33Updated last month
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆30Updated 4 years ago
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- ☆20Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago