srohit0 / CORDIC
CORDIC VLSI-IP for deep learning activation functions
☆13Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for CORDIC
- Design and UVM-TB of RISC -V Microprocessor☆13Updated 4 months ago
- RTL code of some arbitration algorithm☆12Updated 5 years ago
- SoC Based on ARM Cortex-M3☆25Updated 6 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- NoC based MPSoC☆10Updated 10 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆10Updated 4 years ago
- CORE-V MCU UVM Environment and Test Bench☆17Updated 4 months ago
- ☆16Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Implementation of the PCIe physical layer