srohit0 / CORDICLinks
CORDIC VLSI-IP for deep learning activation functions
☆15Updated 6 years ago
Alternatives and similar repositories for CORDIC
Users that are interested in CORDIC are comparing it to the libraries listed below
Sorting:
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆15Updated last year
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆10Updated 3 years ago
- Implementation of the PCIe physical layer☆48Updated last month
- NoC based MPSoC☆11Updated 11 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- ☆30Updated last week
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- ☆19Updated 11 years ago
- ☆20Updated 2 years ago
- Verification IP for Watchdog☆11Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year
- Pipelined FFT/IFFT 64 points processor☆11Updated 11 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆29Updated 2 months ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆14Updated 5 months ago
- SoC Based on ARM Cortex-M3☆32Updated 3 months ago
- ☆29Updated 5 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated 2 weeks ago
- ☆21Updated 5 years ago
- ☆27Updated 5 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 6 years ago