srohit0 / CORDICLinks
CORDIC VLSI-IP for deep learning activation functions
☆15Updated 6 years ago
Alternatives and similar repositories for CORDIC
Users that are interested in CORDIC are comparing it to the libraries listed below
Sorting:
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- NoC based MPSoC☆11Updated 11 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆23Updated last year
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 2 years ago
- ☆10Updated 2 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Pipelined FFT/IFFT 64 points processor☆12Updated 11 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆33Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Router 1 x 3 verilog implementation☆13Updated 3 years ago
- ☆17Updated 10 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆19Updated 10 months ago
- General Purpose AXI Direct Memory Access☆53Updated last year
- 异步FIFO的内部实现☆24Updated 6 years ago
- ☆19Updated 11 years ago
- Implementation of the PCIe physical layer☆45Updated this week
- Verification IP for Watchdog☆11Updated 4 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated 2 weeks ago
- ☆13Updated 2 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 5 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- ☆20Updated 2 years ago
- ☆18Updated 8 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago