abdelazeem201 / SoC-Implementation-of-OpenMSP430-MicrocontrollerLinks
The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 microcontroller family. Due to its characteristics, the openMSP430 was selected to integrate the System on Chip (SOC). This open-core, that will be implemented as an Application Specific Integrated Circuit (ASIC…
☆15Updated 3 years ago
Alternatives and similar repositories for SoC-Implementation-of-OpenMSP430-Microcontroller
Users that are interested in SoC-Implementation-of-OpenMSP430-Microcontroller are comparing it to the libraries listed below
Sorting:
- WISHBONE Interconnect☆11Updated 7 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- To design test bench of the APB protocol☆17Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Various low power labs using sky130☆12Updated 3 years ago
- ☆11Updated 2 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆12Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆20Updated 5 years ago
- Approximate arithmetic circuits for FPGAs☆12Updated 5 years ago
- Verification IP for Watchdog☆11Updated 4 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- ☆20Updated 5 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- Pipelined FFT/IFFT 64 points processor☆12Updated 10 years ago
- Design and UVM-TB of RISC -V Microprocessor☆23Updated last year
- Common SystemVerilog RTL modules for RgGen☆13Updated 3 weeks ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Updated 8 years ago
- ☆12Updated 11 months ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆19Updated 10 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 5 months ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago