abdelazeem201 / SoC-Implementation-of-OpenMSP430-MicrocontrollerLinks
The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 microcontroller family. Due to its characteristics, the openMSP430 was selected to integrate the System on Chip (SOC). This open-core, that will be implemented as an Application Specific Integrated Circuit (ASIC…
☆15Updated 3 years ago
Alternatives and similar repositories for SoC-Implementation-of-OpenMSP430-Microcontroller
Users that are interested in SoC-Implementation-of-OpenMSP430-Microcontroller are comparing it to the libraries listed below
Sorting:
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆13Updated 3 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- ☆41Updated 3 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- ☆11Updated 2 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆27Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Python Tool for UVM Testbench Generation☆53Updated last year
- UART models for cocotb☆29Updated 2 years ago
- A library of verilog and vhdl modules☆15Updated 6 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- ☆10Updated last year
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 3 years ago
- Approximate arithmetic circuits for FPGAs☆12Updated 5 years ago
- A simple DDR3 memory controller☆57Updated 2 years ago
- Pipelined FFT/IFFT 64 points processor☆12Updated 11 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated last month
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- ☆20Updated 5 years ago
- SRAM☆22Updated 4 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 7 months ago
- SoC Based on ARM Cortex-M3☆32Updated 2 months ago
- Engineering Program on RTL Design for FPGA Accelerator☆29Updated 4 years ago