abdelazeem201 / SoC-Implementation-of-OpenMSP430-MicrocontrollerLinks
The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 microcontroller family. Due to its characteristics, the openMSP430 was selected to integrate the System on Chip (SOC). This open-core, that will be implemented as an Application Specific Integrated Circuit (ASIC…
☆16Updated 3 years ago
Alternatives and similar repositories for SoC-Implementation-of-OpenMSP430-Microcontroller
Users that are interested in SoC-Implementation-of-OpenMSP430-Microcontroller are comparing it to the libraries listed below
Sorting:
- To design test bench of the APB protocol☆18Updated 4 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆14Updated 2 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆14Updated 3 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- RTL Design and Verification☆17Updated 4 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- ☆43Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆16Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- ☆21Updated 6 years ago
- WISHBONE Interconnect☆11Updated 8 years ago
- ☆21Updated 5 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated 5 months ago
- Python Tool for UVM Testbench Generation☆54Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- ☆13Updated last year
- APB Logic☆21Updated last week
- The memory model was leveraged from micron.☆24Updated 7 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Implementation of the PCIe physical layer☆57Updated 4 months ago
- Engineering Program on RTL Design for FPGA Accelerator☆31Updated 5 years ago
- Design and UVM-TB of RISC -V Microprocessor☆29Updated last year
- ☆20Updated 3 years ago
- Structured UVM Course☆52Updated last year
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆39Updated 4 months ago