Delta-Sigma modulator (DSM) for fractional phase locked loop.
☆34May 28, 2021Updated 4 years ago
Alternatives and similar repositories for Delta-Sigma-Modulator
Users that are interested in Delta-Sigma-Modulator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 4 years ago
- Delta Sigma DAC FPGA☆47Feb 21, 2025Updated last year
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆11Apr 19, 2022Updated 3 years ago
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆72Apr 9, 2018Updated 7 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- RTL Verilog library for various DSP modules☆95Feb 17, 2022Updated 4 years ago
- All Digital Phase-Locked Loop (ADPLL)☆28Jan 16, 2024Updated 2 years ago
- ☆27Apr 13, 2022Updated 3 years ago
- Utilities for working with Cadence's SKILL/SKILL++ including a unit testing framework.☆47Nov 6, 2020Updated 5 years ago
- ULPI Link Wrapper (USB Phy Interface)☆37May 3, 2020Updated 5 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated 11 months ago
- USB capture IP☆25Jun 6, 2020Updated 5 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆82Jun 12, 2023Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Dec 4, 2020Updated 5 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- USB2.0 Verilog☆20Apr 21, 2019Updated 6 years ago
- All Digital Phase-Locked Loop☆13May 22, 2023Updated 2 years ago
- MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/☆10Feb 4, 2022Updated 4 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆189Oct 6, 2025Updated 5 months ago
- Cadence Virtuoso Design Management System☆36Nov 13, 2022Updated 3 years ago
- All digital PLL☆28Dec 19, 2017Updated 8 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆12Jul 8, 2019Updated 6 years ago
- A collection of phase locked loop (PLL) related projects☆118Jan 18, 2024Updated 2 years ago
- Basic Simulink Blocks for modeling CDRs and PLLs☆15Apr 25, 2020Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆178Aug 8, 2025Updated 7 months ago
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆15Jul 19, 2012Updated 13 years ago
- my cadence/virtuoso/icfb skill functions develloped over the years☆150Feb 27, 2026Updated last month
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆79Apr 11, 2022Updated 3 years ago
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 10 years ago
- Phase locked loop algorithm implemented for grid synchronization.☆24May 18, 2022Updated 3 years ago
- RTL to GDS via Cadence Tools☆16May 17, 2022Updated 3 years ago
- Verilog FPGA code : including experimental DSP audio processor☆13Dec 1, 2020Updated 5 years ago
- A Python parser for hSpice output files and documentation of the hSpice output file format☆24Jan 5, 2026Updated 2 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- RFIC design course developed at Johannes Kepler University, Department for Integrated Circuits☆37Updated this week
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆12Apr 26, 2022Updated 3 years ago
- ☆21Jun 17, 2014Updated 11 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆214Mar 17, 2026Updated last week
- ☆36Dec 10, 2023Updated 2 years ago
- RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K☆43Apr 11, 2024Updated last year
- ☆18Jul 20, 2019Updated 6 years ago