Delta-Sigma modulator (DSM) for fractional phase locked loop.
☆37May 28, 2021Updated 5 years ago
Alternatives and similar repositories for Delta-Sigma-Modulator
Users that are interested in Delta-Sigma-Modulator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 5 years ago
- Delta Sigma DAC FPGA☆47Feb 21, 2025Updated last year
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆14Apr 19, 2022Updated 4 years ago
- A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the fr…☆17Sep 4, 2026Updated 2 months ago
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆74Apr 9, 2018Updated 8 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆99Jun 12, 2023Updated 3 years ago
- Utilities for working with Cadence's SKILL/SKILL++ including a unit testing framework.☆49Nov 6, 2020Updated 6 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- I2S to S/PDIF conversion on SiPeed Tang Nano (GOWIN GW1N-LV1) which aims to convert Nintendo Switch's internal I2S signal.☆41Aug 15, 2020Updated 6 years ago
- Basic Simulink Blocks for modeling CDRs and PLLs☆16Apr 25, 2020Updated 6 years ago
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆59Apr 9, 2026Updated 6 months ago
- ULPI Link Wrapper (USB Phy Interface)☆39May 3, 2020Updated 6 years ago
- All Digital Phase-Locked Loop (ADPLL)☆46Sep 19, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Audio controller (I2S, SPDIF, DAC)☆101Sep 1, 2019Updated 7 years ago
- gm/Id design toolkit: lookup tables, design charts, and automated multicorner sizing of analog circuits☆168Sep 22, 2026Updated last month
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆41Dec 4, 2020Updated 5 years ago
- ☆36Apr 13, 2022Updated 4 years ago
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆21May 24, 2023Updated 3 years ago
- MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/☆10Feb 4, 2022Updated 4 years ago
- USB capture IP☆27Jun 6, 2020Updated 6 years ago
- ☆12Aug 25, 2015Updated 11 years ago
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆68Jan 12, 2021Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- An EDA tool for automatic device sizing using Gm/Id method.☆18Jan 10, 2026Updated 9 months ago
- USB2.0 Verilog☆20Apr 21, 2019Updated 7 years ago
- All digital PLL☆30Dec 19, 2017Updated 8 years ago
- Cadence Virtuoso Design Management System☆40Nov 13, 2022Updated 3 years ago
- Analog Placement Quality Prediction☆26Mar 24, 2023Updated 3 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Oct 2, 2026Updated last month
- Digital audio equalizer created written in Verilog for Altera DE1 SoC FPGA board.☆12Aug 9, 2019Updated 7 years ago
- A simple 5-transistor OTA.☆12Jun 27, 2025Updated last year
- my cadence/virtuoso/icfb skill functions develloped over the years☆173Sep 2, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- USB Type-C Power Delivery FPGA☆34Apr 24, 2026Updated 6 months ago
- All Digital Phase-Locked Loop☆15May 22, 2023Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆123Jan 18, 2024Updated 2 years ago
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆15Jul 19, 2012Updated 14 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆258Oct 6, 2025Updated last year
- ☆18Jul 20, 2019Updated 7 years ago
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆13Apr 26, 2022Updated 4 years ago