Delta-Sigma modulator (DSM) for fractional phase locked loop.
☆36May 28, 2021Updated 5 years ago
Alternatives and similar repositories for Delta-Sigma-Modulator
Users that are interested in Delta-Sigma-Modulator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 5 years ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆12Apr 19, 2022Updated 4 years ago
- Delta Sigma DAC FPGA☆47Feb 21, 2025Updated last year
- Python package for design and simulation of RF phase-locked loops☆15Apr 23, 2022Updated 4 years ago
- RTL Verilog library for various DSP modules☆99Feb 17, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the fr…☆15Apr 14, 2026Updated 3 months ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆74Apr 9, 2018Updated 8 years ago
- Utilities for working with Cadence's SKILL/SKILL++ including a unit testing framework.☆48Nov 6, 2020Updated 5 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- I2S to S/PDIF conversion on SiPeed Tang Nano (GOWIN GW1N-LV1) which aims to convert Nintendo Switch's internal I2S signal.☆41Aug 15, 2020Updated 5 years ago
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆57Apr 9, 2026Updated 3 months ago
- Audio controller (I2S, SPDIF, DAC)☆101Sep 1, 2019Updated 6 years ago
- Basic Simulink Blocks for modeling CDRs and PLLs☆16Apr 25, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆94Jun 12, 2023Updated 3 years ago
- All Digital Phase-Locked Loop (ADPLL)☆38Jan 16, 2024Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆40Dec 4, 2020Updated 5 years ago
- ULPI Link Wrapper (USB Phy Interface)☆38May 3, 2020Updated 6 years ago
- ☆35Apr 13, 2022Updated 4 years ago
- An EDA tool for automatic device sizing using Gm/Id method.☆17Jan 10, 2026Updated 6 months ago
- MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/☆10Feb 4, 2022Updated 4 years ago
- Simulink model for noise shaping SAR ADC☆13Mar 17, 2020Updated 6 years ago
- USB capture IP☆26Jun 6, 2020Updated 6 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- All Digital Phase-Locked Loop☆14May 22, 2023Updated 3 years ago
- All digital PLL☆28Dec 19, 2017Updated 8 years ago
- Code for the paper: Network Decoupling: From Regular to Depthwise Separable Convolutions☆13Dec 9, 2018Updated 7 years ago
- USB2.0 Verilog☆20Apr 21, 2019Updated 7 years ago
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆138Jun 10, 2026Updated last month
- OTFS Modulation FPGA Implementation (Verilog Version)☆16Mar 25, 2025Updated last year
- Cadence Virtuoso Design Management System☆39Nov 13, 2022Updated 3 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆13Jul 8, 2019Updated 7 years ago
- Digital audio equalizer created written in Verilog for Altera DE1 SoC FPGA board.☆12Aug 9, 2019Updated 6 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- A collection of phase locked loop (PLL) related projects☆122Jan 18, 2024Updated 2 years ago
- my cadence/virtuoso/icfb skill functions develloped over the years☆171Jul 7, 2026Updated 3 weeks ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Updated this week
- Analog Placement Quality Prediction☆26Mar 24, 2023Updated 3 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆85Apr 11, 2022Updated 4 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆223Jun 19, 2026Updated last month
- All-Digital Phase-Locked Loops (ADPLL) code in High Speed Integrated Circuit Hardware Description Language (VHDL) for a Field Programmabl…☆13Oct 20, 2025Updated 9 months ago