Delta-Sigma modulator (DSM) for fractional phase locked loop.
☆36May 28, 2021Updated 5 years ago
Alternatives and similar repositories for Delta-Sigma-Modulator
Users that are interested in Delta-Sigma-Modulator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 5 years ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆14Apr 19, 2022Updated 4 years ago
- Python package for design and simulation of RF phase-locked loops☆15Apr 23, 2022Updated 4 years ago
- RTL Verilog library for various DSP modules☆103Feb 17, 2022Updated 4 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆75Apr 9, 2018Updated 8 years ago
- Utilities for working with Cadence's SKILL/SKILL++ including a unit testing framework.☆49Nov 6, 2020Updated 5 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆58Apr 9, 2026Updated 6 months ago
- Audio controller (I2S, SPDIF, DAC)☆101Sep 1, 2019Updated 7 years ago
- Basic Simulink Blocks for modeling CDRs and PLLs☆17Apr 25, 2020Updated 6 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆98Jun 12, 2023Updated 3 years ago
- All Digital Phase-Locked Loop (ADPLL)☆44Sep 19, 2026Updated 3 weeks ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆41Dec 4, 2020Updated 5 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- ULPI Link Wrapper (USB Phy Interface)☆39May 3, 2020Updated 6 years ago
- ☆35Apr 13, 2022Updated 4 years ago
- An EDA tool for automatic device sizing using Gm/Id method.☆18Jan 10, 2026Updated 9 months ago
- MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/☆10Feb 4, 2022Updated 4 years ago
- Simulink model for noise shaping SAR ADC☆14Mar 17, 2020Updated 6 years ago
- USB capture IP☆27Jun 6, 2020Updated 6 years ago
- All Digital Phase-Locked Loop☆15May 22, 2023Updated 3 years ago
- All digital PLL☆31Dec 19, 2017Updated 8 years ago
- Code for the paper: Network Decoupling: From Regular to Depthwise Separable Convolutions☆13Dec 9, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- USB2.0 Verilog☆20Apr 21, 2019Updated 7 years ago
- OTFS Modulation FPGA Implementation (Verilog Version)☆17Mar 25, 2025Updated last year
- gm/Id design toolkit: lookup tables, design charts, and automated multicorner sizing of analog circuits☆162Sep 22, 2026Updated 3 weeks ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆13Jul 8, 2019Updated 7 years ago
- Instrumentation amplifier (analog IP example)☆14Aug 23, 2024Updated 2 years ago
- Cadence Virtuoso Design Management System☆39Nov 13, 2022Updated 3 years ago
- Digital audio equalizer created written in Verilog for Altera DE1 SoC FPGA board.☆12Aug 9, 2019Updated 7 years ago
- my cadence/virtuoso/icfb skill functions develloped over the years☆173Sep 2, 2026Updated last month
- Analog Placement Quality Prediction☆26Mar 24, 2023Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- 基于龙芯 OpenMIPS 实现一个具有 89 条指令的五级流水 CPU,使用 Verilog 语言,使用哈佛结构,包括逻辑移位指令、乘除法指令、加载存储指令、转移指令、协处理器访问指令以及异常相关在内的共89条指令。能够处理数据相关,包含流水线暂停以及延迟槽☆20Mar 8, 2020Updated 6 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Oct 2, 2026Updated 2 weeks ago
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 11 years ago
- All-Digital Phase-Locked Loops (ADPLL) code in High Speed Integrated Circuit Hardware Description Language (VHDL) for a Field Programmabl…☆14Oct 20, 2025Updated 11 months ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆245Oct 6, 2026Updated last week
- Phase locked loop algorithm implemented for grid synchronization.☆26May 18, 2022Updated 4 years ago
- A Real-Time Wave Digital Filter Library for Matlab☆21Jun 18, 2017Updated 9 years ago