Alternatives and similar repositories for riscv-python-model:

Users that are interested in riscv-python-model are comparing it to the libraries listed below

• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆82Updated 4 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 5 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 8 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆79Updated 3 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆64Updated 9 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆62Updated 2 weeks ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated last year
• chipsalliance / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆35Updated this week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆109Updated 2 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆41Updated last month
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆53Updated 2 months ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆77Updated 3 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆66Updated 5 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆62Updated 4 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆61Updated 3 weeks ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆126Updated 5 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆92Updated 3 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆39Updated this week
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆82Updated 3 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆68Updated last week
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆56Updated 3 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 7 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• chipsalliance / uvm-verilator
  ☆81Updated last year
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆156Updated this week
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆155Updated this week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆65Updated this week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆57Updated 2 months ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆98Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 8 months ago