freecores / uart2spi
UART To SPI
☆17Updated 10 years ago
Alternatives and similar repositories for uart2spi:
Users that are interested in uart2spi are comparing it to the libraries listed below
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- development interface mil-std-1553b for system on chip☆19Updated 6 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆18Updated 10 years ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- IP Cores that can be used within Vivado☆25Updated 3 years ago
- I2C controller core☆35Updated 2 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 4 years ago
- ☆28Updated 5 years ago
- USB 2.0 Device IP Core☆53Updated 7 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- Must-have verilog systemverilog modules☆28Updated 2 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆28Updated 9 months ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆46Updated 2 years ago
- SPI-Flash XIP Interface (Verilog)☆35Updated 3 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆24Updated 6 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆22Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- SDRAM controller for MIPSfpga+ system☆21Updated 4 years ago
- Verilog SPI master and slave☆48Updated 9 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆30Updated 4 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆28Updated 3 years ago