freecores / uart2spiLinks
UART To SPI
☆18Updated 11 years ago
Alternatives and similar repositories for uart2spi
Users that are interested in uart2spi are comparing it to the libraries listed below
Sorting:
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- SPI-Flash XIP Interface (Verilog)☆45Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- SDRAM controller for MIPSfpga+ system☆24Updated 5 years ago
- Verilog I2C Slave☆24Updated 11 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- USB 2.0 Device IP Core☆71Updated 8 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- Testbenches for HDL projects☆21Updated last week
- spi memory controller☆22Updated 8 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- Generic AXI master stub☆19Updated 11 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆29Updated 2 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆22Updated 6 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- I2C controller core☆46Updated 2 years ago
- DDR3 SDRAM controller☆18Updated 11 years ago
- Small (Q)SPI flash memory programmer in Verilog☆65Updated 2 years ago
- 1G eth UDP / IP Stack☆10Updated 11 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago