Starrynightzyq/Traffic-lights-ce external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

Starrynightzyq/Traffic-lights-ce

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/Starrynightzyq/Traffic-lights-ce)

Close

Starrynightzyq / Traffic-lights-ceView on GitHubMore

• External links
• Readme badge

基于FPGA的交通灯

☆19Dec 21, 2018Updated 7 years ago

Alternatives and similar repositories for Traffic-lights-ce

Users that are interested in Traffic-lights-ce are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.

• CodeAlanqian / e-clock

  View on GitHub
  基于FPGA实验板的多功能数字时钟。利用Quartus实现设计与仿真
  ☆15May 23, 2023Updated 3 years ago
• Peefy / modulation_2ASK_QPSK

  View on GitHub
  ❤️ This is a Xilinx_FPGA _Spartan6 project for modulation 2ASK QPSK ADC DAC ROM SCI
  ☆18Mar 28, 2018Updated 8 years ago
• JulianKemmerer / Drexel-ECEC575

  View on GitHub
  ☆21Jun 17, 2014Updated 11 years ago
• BBboy01 / 51-Proteus8-traffic-lights-simulation

  View on GitHub
  基于proteus8的51单片机的交通灯仿真
  ☆14Apr 24, 2021Updated 5 years ago
• Embedfire-altera / ebf_ep4ce10_pro_tutorial_code

  View on GitHub
  配套代码《FPGA Verilog开发实战指南——基于Altera EP4CE10》
  ☆14Jul 22, 2021Updated 4 years ago
• Deploy to Railway using AI coding agents - Free Credits Offer • Ad
  Use Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
• DOOKNET / Digital_Clock

  View on GitHub
  基于FPGA的数字时钟（Modelsim仿真）
  ☆28May 22, 2018Updated 8 years ago
• amoudgl / iir-bandstop-filter

  View on GitHub
  Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic
  ☆32May 6, 2017Updated 9 years ago
• Ez4ZheNg / Smart_ParkingLot

  View on GitHub
  毕业设计：基于STM32的智能停车场设计
  ☆21Jan 31, 2020Updated 6 years ago
• freecores / ethernet_tri_mode

  View on GitHub
  10_100_1000 Mbps tri-mode ethernet MAC
  ☆11Jul 17, 2014Updated 11 years ago
• ultraembedded / altor32

  View on GitHub
  AltOr32 - Alternative Lightweight OpenRisc CPU
  ☆13Dec 17, 2015Updated 10 years ago
• DejavuAlex / 2FSK-2PSK-2DPSK-QPSK-code-and-decode

  View on GitHub
  用Verilog语言编写，实现2FSK，2PSK, 2DPSK, QPSK调制解调
  ☆43Mar 15, 2019Updated 7 years ago
• sangwoojun / bluedbm

  View on GitHub
  BlueDBM hw/sw implementation using the bluespecpcie PCIe library
  ☆12Dec 25, 2022Updated 3 years ago
• ultraembedded / ecpix-5

  View on GitHub
  Projects for the ECPiX-5 - a ECP5 FPGA board.
  ☆14Jul 5, 2020Updated 5 years ago
• ahmedshahein / DSP-RTL-Lib

  View on GitHub
  RTL Verilog library for various DSP modules
  ☆97Feb 17, 2022Updated 4 years ago
• GPUs on demand by Runpod - Special Offer Available • Ad
  Run AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
• pku-liang / hlcd-spmm-project

  View on GitHub
  Course Project for High Level Chip Design （高层次芯片设计）
  ☆18Jan 2, 2025Updated last year
• likyoo / awesome-semi-supervised-segmentation

  View on GitHub
  An up-to-date & curated list of awesome semi-supervised segmentation papers, methods & resources.
  ☆13Dec 22, 2023Updated 2 years ago
• ZipCPU / wbsata

  View on GitHub
  Wishbone SATA Controller
  ☆26Oct 16, 2025Updated 7 months ago
• gyd111 / NAND-Flash-controller

  View on GitHub
  MT29F128G based NAND flash controller
  ☆10Jun 17, 2021Updated 4 years ago
• risclite / rv32m-multiplier-and-divider

  View on GitHub
  a multiplier&divider verilog RTL file for RV32M instructions
  ☆14Mar 17, 2020Updated 6 years ago
• hunbfgg / Human-health-monitoring-device

  View on GitHub
  基于STM32的人体健康监测装置
  ☆36Apr 9, 2024Updated 2 years ago
• Starrynightzyq / Fractional-N-DIV

  View on GitHub
  A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop
  ☆16Apr 25, 2021Updated 5 years ago
• Rajandeep / RSA-CRYPTOSYSTEM-using-verilog

  View on GitHub
  ☆12Aug 26, 2016Updated 9 years ago
• SeanZarzycki / openSPARC-FPU

  View on GitHub
  ASIC Design of the openSPARC Floating Point Unit
  ☆17Mar 13, 2017Updated 9 years ago
• Deploy on Railway without the complexity - Free Credits Offer • Ad
  Connect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
• DexWen / LMS-Adaptive-filter

  View on GitHub
  LMS-Adaptive Filter implement using verilog and Matlab
  ☆50Oct 21, 2016Updated 9 years ago
• Verdvana / Async_FIFO

  View on GitHub
  位宽和深度可定制的异步FIFO
  ☆14May 29, 2024Updated 2 years ago
• kaixiangwu / STM32

  View on GitHub
  STM32的笔记和代码 | GPIO | EXTI 外部中断 | TIM 定时器 | USART 串口通信 | IIC 集成电路总线
  ☆19Apr 23, 2023Updated 3 years ago
• ultraembedded / core_ram_tester

  View on GitHub
  AXI-4 RAM Tester Component
  ☆21Aug 5, 2020Updated 5 years ago
• FlorentCLMichel / karatsuba_multiplication_verilog

  View on GitHub
  A simple implementation of the Karatsuba multiplication algorithm
  ☆12Apr 2, 2025Updated last year
• tomverbeure / intel_jtag_primitive_blog

  View on GitHub
  How to use the Intel JTAG primitive without using virtual JTAG
  ☆17Oct 31, 2021Updated 4 years ago
• OpenBanboo / High-Performance-ALU

  View on GitHub
  RTL Design and Implementation of High Performance Algorithm Logic Units
  ☆15Oct 1, 2019Updated 6 years ago
• IObundle / iob-picorv32

  View on GitHub
  IOb_SoC version of the Picorv32 RISC-V Verilog IP core
  ☆14Dec 22, 2025Updated 5 months ago
• ucb-bar / nvdla-wrapper

  View on GitHub
  Wraps the NVDLA project for Chipyard integration
  ☆24Sep 2, 2025Updated 8 months ago
• Deploy to Railway using AI coding agents - Free Credits Offer • Ad
  Use Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
• monotone-RK / FACE

  View on GitHub
  FACE: Fast and Customizable Sorting Accelerator
  ☆11Sep 6, 2016Updated 9 years ago
• wmy367 / Radix-2-division

  View on GitHub
  unsigned Radix-2 SRT division,基2除法
  ☆16May 12, 2015Updated 11 years ago
• p4r4xor / Montgomery1024

  View on GitHub
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆14Nov 28, 2019Updated 6 years ago
• TinyTapeout / tinytapeout-03

  View on GitHub
  ☆16Mar 18, 2024Updated 2 years ago
• Lydaidai / The-car-base-on-FPGA

  View on GitHub
  开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…
  ☆14Mar 10, 2019Updated 7 years ago
• arpitp / ssd-controller

  View on GitHub
  Open Source SSD Controller. NVMe and Lightstor variants
  ☆17May 21, 2014Updated 12 years ago
• travisgoodspeed / 80211scrambler

  View on GitHub
  Tools for working with the 802.11B scrambler when writing Packet-in-Packet exploits.
  ☆20Sep 15, 2013Updated 12 years ago