omega-rg / Cache-Controller
Two Level Cache Controller implementation in Verilog HDL
☆35Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for Cache-Controller
- ☆26Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆28Updated 2 years ago
- A Verilog implementation of a processor cache.☆19Updated 6 years ago
- AXI Interconnect☆45Updated 3 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- AXI4 and AXI4-Lite interface definitions☆83Updated 4 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆70Updated 5 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆30Updated 4 months ago
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆54Updated last year
- ☆15Updated last year
- A verilog implementation for Network-on-Chip☆66Updated 6 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆20Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆14Updated 8 months ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆18Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆121Updated 5 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆38Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆31Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- To design test bench of the APB protocol☆15Updated 3 years ago
- AXI4 BFM in Verilog☆32Updated 7 years ago
- Xilinx AXI VIP example of use☆31Updated 3 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆42Updated last year
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆16Updated 3 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆19Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆35Updated 11 months ago
- round robin arbiter☆66Updated 10 years ago