SystemVerilog & Verilog Module I/O parser and printer
☆26Aug 5, 2026Updated this week
Alternatives and similar repositories for svmodule
Users that are interested in svmodule are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- Python classes to create agnostic wave files for HDL simulator viewer☆13Updated this week
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 4 years ago
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 10 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Nov 12, 2025Updated 8 months ago
- Simple parser for extracting VHDL documentation☆74Jul 12, 2024Updated 2 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- svlib from http://www.verilab.com/resources/svlib/☆28Jun 2, 2020Updated 6 years ago
- ☆14Jan 3, 2018Updated 8 years ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Oct 4, 2023Updated 2 years ago
- ☆18Nov 9, 2022Updated 3 years ago
- UVM interactive debug library☆36Feb 28, 2026Updated 5 months ago
- Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.☆14Nov 29, 2018Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆32Jul 12, 2024Updated 2 years ago
- UVM verification kits which uses YASA as simulation script☆19Dec 10, 2019Updated 6 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆32Jun 13, 2015Updated 11 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆26Oct 15, 2025Updated 9 months ago
- UVM register utility generation by inputting xls table☆39Aug 22, 2023Updated 2 years ago
- hexdump utility by Juergen Weigert; patches submitted to vim☆10Nov 1, 2023Updated 2 years ago
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Hardware Formal Verification☆17Aug 10, 2020Updated 6 years ago
- Graphviz dot to Verilog Finite State Machine (FSM) generator written in Python☆15Feb 3, 2021Updated 5 years ago
- Performance and diagnostic tools for Arm CMN on-chip interconnects☆31Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆471Jul 28, 2026Updated last week
- ☆18Jul 12, 2024Updated 2 years ago
- Code for the second edition of Advanced UVM.☆33Jan 28, 2017Updated 9 years ago
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆38Jun 16, 2026Updated last month
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆481Jun 10, 2026Updated 2 months ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆15May 7, 2022Updated 4 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆103Mar 29, 2024Updated 2 years ago
- verilog_instance.vim: create instantiation of ports from port declaration☆31Mar 13, 2023Updated 3 years ago
- A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COrouti…☆21Dec 24, 2023Updated 2 years ago
- RISC-V Formal in Chisel☆13Apr 9, 2024Updated 2 years ago
- AHB3-Lite Interconnect☆110May 10, 2024Updated 2 years ago
- Just A Really Very Impressive Systemverilog UVM Kit☆18Dec 17, 2020Updated 5 years ago
- A risc-v simulator based on SystrmC☆14Jan 7, 2022Updated 4 years ago