Alternatives and similar repositories for hdlagent

Users that are interested in hdlagent are comparing it to the libraries listed below

• shailja-thakur / AutoChip
  ☆30Updated 4 months ago
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆37Updated last year
• aolofsson / POSH
  ☆44Updated 5 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆25Updated 5 months ago
• pulp-platform / ELAU
  ☆19Updated last year
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆37Updated 3 weeks ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆48Updated 3 weeks ago
• aichipdesign / chipgptv
  Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)
  ☆24Updated last month
• AUCOHL / RTL-Repo
  RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24
  ☆14Updated last year
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated last month
• cornell-brg / pyhdl-eval
  LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs
  ☆16Updated 10 months ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆29Updated 2 weeks ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆34Updated last month
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆95Updated last week
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated last week
• rahulk29 / sram22
  A configurable SRAM generator
  ☆53Updated last week
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆31Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 weeks ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated last month
• pulp-platform / occamy
  A high-efficiency system-on-chip for floating-point compute workloads.
  ☆38Updated 6 months ago
• pku-dasys / cocoon
  An infrastructure for integrated EDA
  ☆41Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆28Updated 2 years ago
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆29Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 5 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 8 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated 2 months ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆39Updated last week
• NVlabs / GL0AM
  GL0AM GPU Accelerated Gate Level Logic Simulator
  ☆22Updated 2 weeks ago
• pulp-platform / svase
  ☆32Updated 6 months ago