Alternatives and similar repositories for hdlagent

Users that are interested in hdlagent are comparing it to the libraries listed below

• shailja-thakur / AutoChip
  ☆40Updated 10 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆32Updated 11 months ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆34Updated 7 months ago
• OpenROAD-Assistant / EDA-Corpus
  Datasets for EDA LLM research
  ☆35Updated 11 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆64Updated this week
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆108Updated 4 months ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆23Updated last week
• pulp-platform / ELAU
  ☆20Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 4 months ago
• opencomputeproject / ODSA-BoW
  Repo for all activity related to the ODSA Bunch of Wires Specification
  ☆28Updated last year
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆43Updated 2 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆38Updated 2 years ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆18Updated 3 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• electronics-and-drives / MLCAD22
  Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"
  ☆14Updated 3 years ago
• pulp-platform / svase
  ☆33Updated last year
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆116Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆96Updated last year
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆72Updated last year
• PrincetonUniversity / OPDB
  OpenPiton Design Benchmark
  ☆28Updated 2 years ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆42Updated last week
• cornell-brg / pyhdl-eval
  LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs
  ☆17Updated last year
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆35Updated 3 weeks ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆54Updated last month
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆29Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago