masc-ucsc / hdlagentLinks
LLM Agent for Hardware Description Language
☆19Updated 3 months ago
Alternatives and similar repositories for hdlagent
Users that are interested in hdlagent are comparing it to the libraries listed below
Sorting:
- ☆44Updated 5 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 3 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43Updated 5 years ago
- ☆19Updated last year
- Library of open source Process Design Kits (PDKs)☆51Updated this week
- ☆32Updated 8 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- ☆35Updated 6 months ago
- Open source process design kit for 28nm open process☆61Updated last year
- Datasets for EDA LLM research☆33Updated 8 months ago
- Fast Symbolic Repair of Hardware Design Code☆26Updated 8 months ago
- A configurable SRAM generator☆54Updated last month
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- sram/rram/mram.. compiler☆42Updated 2 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 10 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆40Updated last month
- Equivalence checking with Yosys☆46Updated 2 weeks ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- CMake based hardware build system☆31Updated last week
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆35Updated 3 weeks ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆24Updated 6 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated 3 weeks ago
- Open Source PHY v2☆30Updated last year
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆16Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 8 months ago