Alternatives and similar repositories for chipgptv:

Users that are interested in chipgptv are comparing it to the libraries listed below

• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆35Updated 2 months ago
• pku-dasys / cocoon
  An infrastructure for integrated EDA
  ☆38Updated last year
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆49Updated 4 months ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆29Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆41Updated 5 months ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆50Updated last year
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆30Updated last year
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆15Updated 4 years ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆86Updated 3 months ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated 9 months ago
• pku-dasys / easymac
  ☆16Updated 3 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆24Updated last year
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆28Updated 4 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆31Updated 3 months ago
• hyoukjun / microswitch-noc
  ☆24Updated 5 years ago
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 3 years ago
• shailja-thakur / AutoChip
  ☆24Updated 2 months ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆21Updated 3 years ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆15Updated last month
• GATECH-EIC / LLM4HWDesign_Starting_Toolkit
  LLM4HWDesign Starting Toolkit
  ☆17Updated 4 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆15Updated last year
• daitoto / EDA-wiki
  EDA wiki
  ☆51Updated last year
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆43Updated last year
• The-OpenROAD-Project / asap5
  ☆21Updated last year
• VeriGOOD-ML / public
  ☆53Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆42Updated last month