Alternatives and similar repositories for chipgptv

Users that are interested in chipgptv are comparing it to the libraries listed below

• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆53Updated 11 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆150Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆59Updated 6 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆54Updated 6 months ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆28Updated 7 months ago
• yaoxufeng / RTLRewriter-Bench
  ☆41Updated last year
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆44Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated 6 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆19Updated last year
• IPRC-DIP / CodeV
  ☆53Updated 3 months ago
• UIUC-ChenLab / Chrysalis-HLS
  ☆15Updated last year
• shailja-thakur / VGen
  ☆193Updated last year
• pku-dasys / easymac
  ☆16Updated 3 years ago
• zshi0616 / python-deepgate
  ☆26Updated last year
• pku-dasys / cocoon
  An infrastructure for integrated EDA
  ☆42Updated 2 years ago
• hkust-zhiyao / RTL-Coder
  A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
  ☆240Updated 10 months ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆42Updated last year
• stable-lab / MAGE
  MAGE: A Multi-Agent Engine for Automated RTL Code Generation
  ☆75Updated 8 months ago
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆70Updated 6 months ago
• AutoBench / AutoBench
  ☆33Updated 8 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆55Updated 11 months ago
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆33Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆29Updated last year
• DfX-NYUAD / LLM4IC
  LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
  ☆33Updated last year
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆13Updated last year
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆30Updated 10 months ago
• magicYang1573 / llm-hardware-test-generation
  ☆33Updated last year
• QiMeng-IPRC / QiMeng-cpu-v1
  ☆26Updated 7 months ago
• GATECH-EIC / mg-verilog
  ☆51Updated last year