NVlabs / cvdp_benchmarkLinks
☆60Updated last week
Alternatives and similar repositories for cvdp_benchmark
Users that are interested in cvdp_benchmark are comparing it to the libraries listed below
Sorting:
- Verilog evaluation benchmark for large language model☆303Updated 3 weeks ago
- ☆179Updated 9 months ago
- An open-source benchmark for generating design RTL with natural language☆126Updated 9 months ago
- ☆51Updated 5 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆215Updated 6 months ago
- ☆84Updated last month
- ☆25Updated 4 months ago
- ☆14Updated 11 months ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆53Updated 4 months ago
- ☆74Updated 2 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆36Updated 9 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆51Updated 2 months ago
- ☆52Updated 2 months ago
- ☆39Updated 2 years ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆22Updated 4 months ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆43Updated 2 months ago
- Open-source RTL logic simulator with CUDA acceleration☆201Updated this week
- ☆22Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆59Updated 2 weeks ago
- ☆88Updated last month
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆131Updated 3 weeks ago
- ☆70Updated 4 months ago
- ☆36Updated last year
- ☆179Updated 5 months ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆15Updated 2 years ago
- ☆105Updated 5 years ago
- Fast Symbolic Repair of Hardware Design Code☆25Updated 6 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated 2 weeks ago
- This is a python repo for flattening Verilog☆18Updated 3 months ago
- ☆47Updated last month