NVlabs / cvdp_benchmarkLinks
☆91Updated last week
Alternatives and similar repositories for cvdp_benchmark
Users that are interested in cvdp_benchmark are comparing it to the libraries listed below
Sorting:
- Verilog evaluation benchmark for large language model☆331Updated 3 months ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆67Updated 6 months ago
- ☆186Updated last year
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆232Updated 8 months ago
- An open-source benchmark for generating design RTL with natural language☆135Updated 11 months ago
- ☆14Updated last year
- ☆30Updated 6 months ago
- ☆49Updated last month
- ☆49Updated last year
- ☆74Updated 7 months ago
- ☆41Updated last year
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆50Updated 10 months ago
- ☆38Updated 7 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 5 months ago
- ☆91Updated 4 months ago
- ☆245Updated last year
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆65Updated 4 months ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆14Updated last year
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)☆30Updated last month
- Fix syntax errors of LLM-generated RTL☆39Updated last year
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆39Updated last year
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆136Updated 3 months ago
- Machine-Learning Accelerator System Exploration Tools☆179Updated 3 weeks ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆26Updated 6 months ago
- ☆77Updated 4 months ago
- ☆54Updated 5 months ago
- ☆150Updated 2 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆30Updated 2 years ago
- This is a python repo for flattening Verilog☆20Updated 5 months ago
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆23Updated last year