Alternatives and similar repositories for MCP4EDA

Users that are interested in MCP4EDA are comparing it to the libraries listed below

• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆37Updated 5 years ago
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆42Updated 2 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 5 years ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆135Updated 11 months ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated 5 months ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆191Updated 5 years ago
• ncsu-eda / FreePDK3
  ☆178Updated 4 years ago
• laiyao1 / AnalogCoder
  ☆88Updated 2 months ago
• The-OpenROAD-Project / asap7
  ☆201Updated 7 months ago
• NVlabs / VerilogCoder
  ☆74Updated 7 months ago
• NVlabs / INSTA
  ☆88Updated 4 months ago
• parallaxsw / OpenSTA
  ☆90Updated last week
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆85Updated 6 months ago
• EECS150 / asic_labs_sp22
  ☆26Updated 3 years ago
• vaughnbetz / COFFE
  ☆44Updated last year
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆79Updated 4 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆79Updated 4 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• AUCOHL / RTL-Repo
  RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24
  ☆23Updated last year
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 2 months ago
• The-OpenROAD-Project / asap5
  ☆35Updated 2 years ago
• zshi0616 / python-deepgate
  ☆23Updated last year
• ABKGroup / PROBE3.0
  ☆47Updated last year
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆66Updated last year
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆50Updated 10 months ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆271Updated 2 weeks ago
• pkuzjx / eda-collection
  ☆106Updated 5 years ago
• magical-eda / OpenSAR
  ☆16Updated 3 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆58Updated 5 months ago