NellyW8 / MCP4EDALinks
This is the Github Repo for the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization. MCP server for a collection of open-source EDA tools
☆26Updated last month
Alternatives and similar repositories for MCP4EDA
Users that are interested in MCP4EDA are comparing it to the libraries listed below
Sorting:
- ☆65Updated 6 months ago
- SRAM☆22Updated 5 years ago
- This is a python repo for flattening Verilog☆19Updated 4 months ago
- A configurable SRAM generator☆54Updated last month
- ☆87Updated last week
- Open source process design kit for 28nm open process☆61Updated last year
- SRAM Design using OpenSource Applications☆22Updated 4 years ago
- An open-source benchmark for generating design RTL with natural language☆131Updated 10 months ago
- sram/rram/mram.. compiler☆42Updated 2 years ago
- ☆183Updated 11 months ago
- ☆42Updated 3 years ago
- ☆172Updated 4 years ago
- ☆37Updated 6 months ago
- ☆86Updated 3 months ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆84Updated 4 months ago
- ☆77Updated 3 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆78Updated 4 years ago
- ☆105Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- ☆53Updated 5 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- A Verilog implementation of a processor cache.☆28Updated 7 years ago
- Python wrapper for verilator model☆88Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- ☆188Updated 6 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆30Updated 3 months ago
- SystemVerilog FSM generator☆32Updated last year