This is the Github Repo for the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization. MCP server for a collection of open-source EDA tools
☆102Jul 29, 2025Updated last year
Alternatives and similar repositories for MCP4EDA
Users that are interested in MCP4EDA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆41Jul 12, 2025Updated last year
- This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generati…☆29Sep 25, 2025Updated 10 months ago
- Datasets for EDA LLM research☆46Jan 17, 2025Updated last year
- ☆32Jun 18, 2026Updated last month
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆32Jul 24, 2025Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Pytorch Code for FedHyper☆11Aug 28, 2024Updated last year
- LLM4HWDesign Starting Toolkit☆20Oct 4, 2024Updated last year
- ☆16Jun 30, 2024Updated 2 years ago
- ☆20Aug 8, 2024Updated 2 years ago
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆57May 21, 2025Updated last year
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆374Feb 9, 2025Updated last year
- ☆30Jun 25, 2024Updated 2 years ago
- An open-source benchmark for generating design RTL with natural language☆218Nov 8, 2024Updated last year
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆43Jul 9, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Timing prediction dataset download and instructions.☆19Jun 7, 2023Updated 3 years ago
- A Python library that reads LEF and DEF files, extract the RC parasitics and generate their corresponding SPEF file.☆19Sep 23, 2020Updated 5 years ago
- RTL-to-Vector-to-GDS☆86Apr 2, 2026Updated 4 months ago
- pyslang-mcp is a read-only Model Context Protocol server for compiler-backed Verilog and SystemVerilog analysis. It uses pyslang to parse…☆20Jun 14, 2026Updated last month
- ☆25May 8, 2025Updated last year
- ☆60Mar 10, 2025Updated last year
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆33Oct 20, 2024Updated last year
- OpenROAD's Chatbot Assistant☆45Updated this week
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆23Jan 28, 2026Updated 6 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification☆36Dec 11, 2025Updated 8 months ago
- Compiler Explorer for RTL: synthesize Verilog with Yosys and explore timing paths, logic depth, and fanin/fanout interactively☆42Aug 1, 2026Updated last week
- Digital HDL Design Full-stack Agents☆180Jul 28, 2026Updated last week
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆31Feb 24, 2026Updated 5 months ago
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 3 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- Verilog evaluation benchmark for large language model☆460Jul 14, 2025Updated last year
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆41May 17, 2024Updated 2 years ago
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆34May 4, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆34Jun 5, 2024Updated 2 years ago
- ☆34Jul 3, 2026Updated last month
- This github repository summarizes relevant papers for shift left techniques in electronic design automation (EDA).☆34Jun 17, 2026Updated last month
- Artificial Netlist Generator☆48Mar 19, 2024Updated 2 years ago
- LLM-aided Hardware Design and Verification☆37May 11, 2026Updated 3 months ago
- ☆116Jun 22, 2026Updated last month
- ☆109Jun 20, 2025Updated last year