Alternatives and similar repositories for CodeV

Users that are interested in CodeV are comparing it to the libraries listed below

• Qimeng-ICT / Qimeng-1
  ☆21Updated 2 months ago
• hkust-zhiyao / RTL-Coder
  A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
  ☆210Updated 5 months ago
• magicYang1573 / llm-hardware-test-generation
  ☆31Updated last year
• stable-lab / MAGE
  MAGE: A Multi-Agent Engine for Automated RTL Code Generation
  ☆52Updated 3 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆121Updated 8 months ago
• GATECH-EIC / mg-verilog
  ☆46Updated 9 months ago
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆43Updated 7 months ago
• shailja-thakur / VGen
  ☆171Updated 9 months ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆17Updated 3 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆52Updated last month
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆52Updated last month
• NVlabs / verilog-eval
  Verilog evaluation benchmark for large language model
  ☆288Updated 5 months ago
• aichipdesign / chipgptv
  Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)
  ☆24Updated last month
• UIUC-ChenLab / Chrysalis-HLS
  ☆14Updated 10 months ago
• shailja-thakur / AutoChip
  ☆30Updated 4 months ago
• DfX-NYUAD / LLM4IC
  LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
  ☆27Updated last year
• ACADLab / SPICEPilot
  This repository hosts the information of SPICEPilot: a training free LLM data-augmentation, new bench marking and future road-map.
  ☆19Updated last month
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆34Updated 8 months ago
• Thinklab-SJTU / Awesome-LLM4EDA
  ☆217Updated last year
• yaoxufeng / RTLRewriter-Bench
  ☆34Updated last year
• NVlabs / RTLFixer
  Fix syntax errors of LLM-generated RTL
  ☆35Updated last year
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• GATECH-EIC / LLM4HWDesign_Starting_Toolkit
  LLM4HWDesign Starting Toolkit
  ☆17Updated 9 months ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆18Updated 2 months ago
• AutoBench / AutoBench
  ☆24Updated 3 months ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆30Updated 10 months ago
• AUCOHL / RTL-Repo
  RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24
  ☆14Updated last year
• OpenROAD-Assistant / EDA-Corpus
  Datasets for EDA LLM research
  ☆30Updated 6 months ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆51Updated 9 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆19Updated last year