IPRC-DIP / CodeVLinks
☆53Updated 3 months ago
Alternatives and similar repositories for CodeV
Users that are interested in CodeV are comparing it to the libraries listed below
Sorting:
- ☆33Updated last year
- ☆192Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆75Updated 8 months ago
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆53Updated 11 months ago
- An open-source benchmark for generating design RTL with natural language☆150Updated last year
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆240Updated 10 months ago
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆27Updated last year
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆30Updated 5 months ago
- ☆33Updated 8 months ago
- ☆51Updated last year
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆26Updated 7 months ago
- ☆39Updated 9 months ago
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)☆34Updated last week
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆59Updated 6 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆29Updated 8 months ago
- ☆15Updated last year
- Fix syntax errors of LLM-generated RTL☆39Updated last year
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆44Updated last year
- FSA: Fusing FlashAttention within a Single Systolic Array☆68Updated 4 months ago
- ☆41Updated last year
- ☆31Updated 8 months ago
- This is a python repo for flattening Verilog☆20Updated 7 months ago
- ☆54Updated 6 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆33Updated last year
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆27Updated last year
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- ACM TODAES Best Paper Award, 2022☆32Updated 2 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆115Updated last year
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆35Updated 6 months ago
- Verilog evaluation benchmark for large language model☆350Updated 4 months ago