Alternatives and similar repositories for CodeV

Users that are interested in CodeV are comparing it to the libraries listed below

• magicYang1573 / llm-hardware-test-generation
  ☆31Updated last year
• hkust-zhiyao / RTL-Coder
  A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
  ☆232Updated 8 months ago
• stable-lab / MAGE
  MAGE: A Multi-Agent Engine for Automated RTL Code Generation
  ☆67Updated 6 months ago
• GATECH-EIC / mg-verilog
  ☆49Updated last year
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆135Updated 11 months ago
• shailja-thakur / VGen
  ☆184Updated last year
• Qimeng-ICT / Qimeng-1
  ☆24Updated 5 months ago
• AUCOHL / RTL-Repo
  RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24
  ☆23Updated last year
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆50Updated 10 months ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆26Updated 6 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆54Updated 5 months ago
• pku-liang / OriGen
  OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)
  ☆26Updated last year
• aichipdesign / chipgptv
  Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)
  ☆30Updated 4 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆58Updated 5 months ago
• VCA-EPFL / FSA
  FSA: Fusing FlashAttention within a Single Systolic Array
  ☆54Updated 2 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆39Updated last year
• UIUC-ChenLab / Chrysalis-HLS
  ☆14Updated last year
• HPAI-BSC / TuRTLe
  TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)
  ☆30Updated last month
• shailja-thakur / AutoChip
  ☆38Updated 7 months ago
• NVlabs / RTLFixer
  Fix syntax errors of LLM-generated RTL
  ☆39Updated last year
• NVlabs / verilog-eval
  Verilog evaluation benchmark for large language model
  ☆331Updated 3 months ago
• ACADLab / SPICEPilot
  This repository hosts the information of SPICEPilot: a training free LLM data-augmentation, new bench marking and future road-map.
  ☆21Updated 5 months ago
• Thinklab-SJTU / Awesome-LLM4EDA
  ☆245Updated last year
• AutoBench / AutoBench
  ☆28Updated 6 months ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated 2 years ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆19Updated last year
• mit-han-lab / spatten
  [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
  ☆112Updated last year
• Intelligent-Computing-Research-Group / HaVen
  [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers
  ☆23Updated 3 months ago
• hkust-zhiyao / SpecLLM
  SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
  ☆15Updated last year
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆32Updated last year