☆54Sep 4, 2025Updated 6 months ago
Alternatives and similar repositories for CodeV
Users that are interested in CodeV are comparing it to the libraries listed below
Sorting:
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆27May 4, 2025Updated 10 months ago
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆38Jul 9, 2025Updated 8 months ago
- [AAAI 2025] The official code of the paper "InverseCoder: Unleashing the Power of Instruction-Tuned Code LLMs with Inverse-Instruct"(http…☆14Jul 10, 2024Updated last year
- ☆42Jan 6, 2026Updated 2 months ago
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆34Jun 5, 2024Updated last year
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆34Apr 13, 2025Updated 11 months ago
- ☆22Dec 7, 2023Updated 2 years ago
- Verilog evaluation benchmark for large language model☆386Jul 14, 2025Updated 8 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆265Feb 9, 2025Updated last year
- ☆55Oct 8, 2024Updated last year
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated last year
- ☆14Oct 8, 2024Updated last year
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆46May 21, 2025Updated 10 months ago
- Equivalence checking with Yosys☆58Mar 4, 2026Updated 2 weeks ago
- This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generati…☆21Sep 25, 2025Updated 5 months ago
- ☆20Apr 9, 2025Updated 11 months ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆43May 29, 2025Updated 9 months ago
- ☆45May 18, 2024Updated last year
- ☆141Mar 11, 2026Updated last week
- LLM4HWDesign Starting Toolkit☆19Oct 4, 2024Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆38Jun 17, 2025Updated 9 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆144Jul 23, 2025Updated 7 months ago
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated last year
- Taiwei-3D-Flow☆41Mar 2, 2026Updated 2 weeks ago
- ☆43Dec 16, 2025Updated 3 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)☆40Feb 23, 2026Updated 3 weeks ago
- coursier CLI launchers☆14Mar 12, 2026Updated last week
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- This repo includes XiangShan's function units☆30Feb 14, 2026Updated last month
- ☆200Oct 17, 2024Updated last year
- ☆268Jul 8, 2024Updated last year
- ☆39Dec 28, 2023Updated 2 years ago
- Noq is an online logic puzzle solver using Python and clasp!☆12Oct 12, 2025Updated 5 months ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆91Apr 11, 2025Updated 11 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆50Jan 20, 2026Updated 2 months ago
- ☆11Apr 16, 2023Updated 2 years ago