☆88Jan 7, 2023Updated 3 years ago
Alternatives and similar repositories for rapid-design-methods-for-developing-hardware-accelerators
Users that are interested in rapid-design-methods-for-developing-hardware-accelerators are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 6 months ago
- ☆13Feb 13, 2021Updated 5 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- Bring FPGA accelerators as a resources available through Docker containers for the OpenStack users.☆16Nov 7, 2022Updated 3 years ago
- TLUT tool flow for parameterised configurations for FPGAs☆16Aug 5, 2024Updated last year
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Jan 28, 2025Updated last year
- ☆22Feb 18, 2025Updated last year
- Towards Hardware and Software Continuous Integration☆13Jun 8, 2020Updated 5 years ago
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- Layout, rendering ELK Graph generated by easysoc-firrtl, and display the graph as an interactive diagram to represent Chisel generated Fi…☆12Apr 1, 2022Updated 3 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 10 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆75Nov 15, 2015Updated 10 years ago
- Aiming at an AI Chip based on RISC-V and NVDLA.☆21Mar 8, 2018Updated 8 years ago
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆14Aug 30, 2023Updated 2 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 6 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆149Dec 25, 2019Updated 6 years ago
- ☆68Jan 7, 2023Updated 3 years ago
- Open Programmable Acceleration Engine☆270Jul 25, 2025Updated 7 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆295Oct 30, 2025Updated 4 months ago
- Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures☆11Apr 23, 2019Updated 6 years ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆314Mar 6, 2026Updated 2 weeks ago
- RISC-V GPGPU☆36Mar 6, 2020Updated 6 years ago
- ☆12May 20, 2021Updated 4 years ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆245Apr 29, 2024Updated last year
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- ☆14Feb 14, 2022Updated 4 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆176Jun 18, 2020Updated 5 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆18Aug 1, 2019Updated 6 years ago
- ☆11Dec 18, 2017Updated 8 years ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆340Apr 20, 2024Updated last year
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Sep 22, 2018Updated 7 years ago
- Video Effects on VGA☆15Jan 7, 2019Updated 7 years ago
- The source code that empowers OpenROAD Cloud☆12Jun 29, 2020Updated 5 years ago
- ☆18Jul 9, 2025Updated 8 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Nov 22, 2019Updated 6 years ago