rameloni / tywaves-chiselLinks
A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code to values dumped by simulators is now possible thanks to Tywaves!
☆46Updated 8 months ago
Alternatives and similar repositories for tywaves-chisel
Users that are interested in tywaves-chisel are comparing it to the libraries listed below
Sorting:
- high-performance RTL simulator☆168Updated last year
- A dynamic verification library for Chisel.☆152Updated 8 months ago
- (System)Verilog to Chisel translator☆115Updated 3 years ago
- ☆20Updated 4 months ago
- ☆40Updated last month
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆14Updated 5 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆101Updated last month
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- ☆96Updated last year
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆122Updated this week
- Advanced Architecture Labs with CVA6☆65Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆86Updated last week
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- Chisel RISC-V Vector 1.0 Implementation☆103Updated 2 months ago
- An energy-efficient RISC-V floating-point compute cluster.☆91Updated this week
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- Hardware generator debugger☆74Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆204Updated 2 months ago
- Equivalence checking with Yosys☆45Updated this week
- A Rocket-based RISC-V superscalar in-order core☆33Updated 2 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆85Updated last year
- Vector Acceleration IP core for RISC-V*☆180Updated 2 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆112Updated last week
- A Fast, Low-Overhead On-chip Network☆214Updated last week
- A tool for synthesizing Verilog programs☆95Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆65Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- RISC-V Formal Verification Framework☆142Updated last month