Alternatives and similar repositories for tywaves-chisel

Users that are interested in tywaves-chisel are comparing it to the libraries listed below

• ucsc-vama / essent
  high-performance RTL simulator
  ☆185Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆159Updated last year
• chipsalliance / espresso
  ☆41Updated last month
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆116Updated 2 months ago
• openhwgroup / cv-hpdcache-verif
  Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
  ☆19Updated last week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆176Updated last week
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 10 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated last month
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆54Updated this week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆224Updated 2 months ago
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆160Updated this week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆126Updated 3 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆121Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆225Updated 10 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆98Updated last year
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆122Updated 2 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆111Updated 2 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆89Updated last year
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆108Updated 4 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆187Updated this week
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆128Updated 2 years ago
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆252Updated 3 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated 2 months ago