Alternatives and similar repositories for sram22:

Users that are interested in sram22 are comparing it to the libraries listed below

• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆50Updated 10 months ago
• pulp-platform / svase
  ☆31Updated 2 months ago
• pulp-platform / cheshire-ihp130-o
  ☆33Updated 5 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆35Updated 2 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆47Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆44Updated 7 months ago
• rahulk29 / sram22_sky130_macros
  SKY130 SRAM macros generated by SRAM 22
  ☆12Updated 2 weeks ago
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆31Updated last year
• ReuelReuben / vsdSRAM
  SRAM
  ☆21Updated 4 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆24Updated last year
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• The-OpenROAD-Project / asap5
  ☆22Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• snishizawa / libretto
  Characterizer
  ☆21Updated 6 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆76Updated 11 months ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆25Updated 4 years ago
• fabianschuiki / potstill
  An open source generator for standard cell based memories.
  ☆13Updated 8 years ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆35Updated this week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆79Updated last week
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆102Updated 11 months ago
• aolofsson / POSH
  ☆41Updated 5 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆31Updated 2 weeks ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 4 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 8 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago