rahulk29 / sram22Links
A configurable SRAM generator
☆53Updated this week
Alternatives and similar repositories for sram22
Users that are interested in sram22 are comparing it to the libraries listed below
Sorting:
- Open source process design kit for 28nm open process☆59Updated last year
- ☆32Updated 6 months ago
- An automatic clock gating utility☆50Updated 2 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆49Updated 5 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- ☆37Updated 3 years ago
- SKY130 SRAM macros generated by SRAM 22☆16Updated this week
- Characterizer☆28Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- sram/rram/mram.. compiler☆35Updated last year
- Library of open source Process Design Kits (PDKs)☆48Updated 2 weeks ago
- ☆44Updated 5 years ago
- ☆47Updated 3 months ago
- YosysHQ SVA AXI Properties☆41Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆85Updated last year
- ☆33Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated last month
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆56Updated 3 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆112Updated last year
- SRAM☆22Updated 4 years ago
- Open Source PHY v2☆29Updated last year
- ☆19Updated last year
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year