Alternatives and similar repositories for sram22:

Users that are interested in sram22 are comparing it to the libraries listed below

• rahulk29 / sram22_sky130_macros
  SKY130 SRAM macros generated by SRAM 22
  ☆16Updated this week
• pulp-platform / svase
  ☆31Updated 3 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆40Updated 2 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆53Updated 11 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆46Updated last week
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆35Updated 2 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• aolofsson / POSH
  ☆43Updated 5 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆27Updated this week
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 4 years ago
• snishizawa / libretto
  Characterizer
  ☆22Updated 8 months ago
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆33Updated last year
• pulp-platform / cheshire-ihp130-o
  ☆35Updated 3 weeks ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆27Updated 11 months ago
• fabianschuiki / potstill
  An open source generator for standard cell based memories.
  ☆13Updated 8 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 5 months ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆37Updated this week
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆25Updated 2 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 9 months ago
• pulp-platform / axi_llc
  ☆25Updated last week
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 11 months ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆29Updated this week