rahulk29 / sram22
A configurable SRAM generator
☆41Updated last week
Related projects: ⓘ
- Open source process design kit for 28nm open process☆38Updated 4 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆38Updated last year
- An automatic clock gating utility☆40Updated 2 months ago
- ☆35Updated 2 years ago
- ☆28Updated 2 weeks ago
- sram/rram/mram.. compiler☆26Updated last year
- AMC: Asynchronous Memory Compiler☆44Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆38Updated 4 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆30Updated last year
- slang-based frontend for Yosys☆28Updated this week
- Open Source PHY v2☆23Updated 4 months ago
- Library of open source Process Design Kits (PDKs)☆21Updated this week
- For contributions of Chisel IP to the chisel community.☆55Updated 7 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆66Updated 4 months ago
- ☆18Updated last year
- SRAM☆19Updated 4 years ago
- Hardware generator debugger☆71Updated 7 months ago
- ☆51Updated 2 years ago
- ☆37Updated 4 years ago
- Chisel Cheatsheet☆31Updated last year
- An open source PDK using TIGFET 10nm devices.☆42Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆44Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆72Updated 5 months ago
- Python wrapper for verilator model☆76Updated 7 months ago
- Equivalence checking with Yosys☆29Updated this week
- ☆19Updated this week
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 2 months ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆11Updated 6 months ago
- The RTL source for AnyCore RISC-V☆29Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆48Updated last month