shioya-lab-public / surgefuzz
SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs (ICCAD 2023)
☆19Updated 3 months ago
Alternatives and similar repositories for surgefuzz:
Users that are interested in surgefuzz are comparing it to the libraries listed below
- ☆15Updated 3 years ago
- Project Repo for the Simulator Independent Coverage Research☆18Updated 2 years ago
- Fuzzing for SpinalHDL☆16Updated 2 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- ☆12Updated 6 months ago
- ☆23Updated 2 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆15Updated 3 years ago
- Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation☆25Updated last year
- The SoC used for the beta phase of Hack@DAC 2018.☆17Updated 4 years ago
- Code repository for Coppelia tool☆23Updated 4 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆61Updated last week
- All the tools you need to reproduce the CellIFT paper experiments☆18Updated last month
- A port of the RIPE suite to RISC-V.☆29Updated 6 years ago
- This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).☆26Updated 4 years ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆23Updated last year
- rfuzz: coverage-directed fuzzing for RTL research platform☆105Updated 2 years ago
- Testing processors with Random Instruction Generation☆35Updated 2 weeks ago
- ☆82Updated 10 months ago
- ☆80Updated 2 years ago
- Medusa Repository: Transynther tool and Medusa Attack☆21Updated 4 years ago
- Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores☆13Updated 2 weeks ago
- BTOR2 MLIR project☆25Updated last year
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 5 years ago
- Pre-Silicon Hardware Fuzzing Toolkit☆55Updated last month
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆20Updated 2 months ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆12Updated 2 weeks ago
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆17Updated 2 years ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆86Updated last month
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆17Updated last year
- ☆17Updated 9 months ago