efeslab / asplos22-hardware-debugging-artifact
☆11Updated 8 months ago
Alternatives and similar repositories for asplos22-hardware-debugging-artifact:
Users that are interested in asplos22-hardware-debugging-artifact are comparing it to the libraries listed below
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆17Updated last year
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆17Updated 4 months ago
- ☆17Updated 7 months ago
- ☆17Updated 8 months ago
- ☆11Updated last year
- ☆9Updated 9 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- Automated Repair of Verilog Hardware Descriptions☆27Updated last month
- ILA Model Database☆22Updated 4 years ago
- Random Generator of Btor2 Files☆9Updated last year
- Project Repo for the Simulator Independent Coverage Research☆18Updated last year
- Code repository for Coppelia tool☆22Updated 4 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆16Updated 3 months ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆14Updated last month
- RTLCheck☆19Updated 6 years ago
- Memory consistency model checking and test generation library.☆14Updated 8 years ago
- The SoC used for the beta phase of Hack@DAC 2018.☆17Updated 4 years ago
- ☆12Updated 3 years ago
- Fast Symbolic Repair of Hardware Design Code☆22Updated last month
- RISC-V Formal in Chisel☆10Updated 10 months ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 5 years ago
- Hardware Model Checker☆32Updated this week
- CleanupSpec (MICRO-2019)☆17Updated 4 years ago
- A generic parser and tool package for the BTOR2 format.☆41Updated 2 months ago
- ☆11Updated 4 years ago
- ☆18Updated 5 years ago
- Recent papers related to hardware formal verification.☆64Updated last year
- This is a python repo for flattening Verilog☆15Updated last month
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆13Updated 6 years ago