Alternatives and similar repositories for asplos22-hardware-debugging-artifact

Users that are interested in asplos22-hardware-debugging-artifact are comparing it to the libraries listed below

• dian-lun-lin / GenFuzz
  GPU-enabled Hardware Fuzzer using Genetic Algorithm
  ☆19Updated 2 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 5 years ago
• hammad-a / verilog_repair
  Automated Repair of Verilog Hardware Descriptions
  ☆35Updated 10 months ago
• efeslab / hardware-bugbase
  ☆20Updated last year
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆74Updated this week
• zilongwang123 / LeaVe
  A tool for checking the contract satisfaction for hardware designs
  ☆11Updated 2 weeks ago
• iscas-tis / CHA
  ☆19Updated last year
• yaohsiaopid / rtl2uspec
  ☆11Updated 4 months ago
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated 2 years ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆43Updated 2 months ago
• melver / mc2lib
  Memory consistency model checking and test generation library.
  ☆15Updated 9 years ago
• UCLA-SEAL / HeteroGen
  HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)
  ☆17Updated last year
• hkustgz-zhang-lab / HW-Formal-Paper
  Recent papers related to hardware formal verification.
  ☆74Updated 2 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆33Updated 7 months ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆11Updated last week
• ekiwi / simulator-independent-coverage
  Project Repo for the Simulator Independent Coverage Research
  ☆21Updated 2 years ago
• RafaelTupynamba / SMTSampler
  SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints
  ☆31Updated 6 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 4 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆23Updated 7 years ago
• hackdac / hackdac_2018_beta
  The SoC used for the beta phase of Hack@DAC 2018.
  ☆17Updated 5 years ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆17Updated 6 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆91Updated last week
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 5 months ago
• comsec-group / encarsia
  ☆25Updated 7 months ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆26Updated 3 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆36Updated 3 years ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• achieve-lab / assertion_data_for_LLM
  ☆21Updated 9 months ago