ycunxi / FLowGen-CNNs-DAC18Links
☆16Updated 7 years ago
Alternatives and similar repositories for FLowGen-CNNs-DAC18
Users that are interested in FLowGen-CNNs-DAC18 are comparing it to the libraries listed below
Sorting:
- ☆20Updated 3 years ago
- Awesome machine learning for logic synthesis☆29Updated 3 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- ☆15Updated 2 years ago
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆28Updated 5 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆36Updated last year
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆14Updated last year
- Simple Python interface for ABC☆25Updated 2 years ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated 10 months ago
- GPU-based logic synthesis tool☆92Updated 2 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆135Updated 3 months ago
- DATC RDF☆50Updated 5 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆53Updated 9 months ago
- Collection of digital hardware modules & projects (benchmarks)☆65Updated last week
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 6 months ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆24Updated 3 years ago
- A logic synthesis tool☆82Updated last month
- ☆13Updated 2 years ago
- EPFL logic synthesis benchmarks☆214Updated 3 weeks ago
- Routing Visualization for Physical Design☆19Updated 6 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 5 months ago
- Research paper based on or related to ABC.☆55Updated 3 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆32Updated last year
- ☆18Updated 4 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆34Updated 5 months ago
- ☆27Updated last year
- DATC Robust Design Flow.☆36Updated 5 years ago
- GNN-RE datasets for circuit recognition☆54Updated 2 years ago