ycunxi / FLowGen-CNNs-DAC18Links
☆16Updated 7 years ago
Alternatives and similar repositories for FLowGen-CNNs-DAC18
Users that are interested in FLowGen-CNNs-DAC18 are comparing it to the libraries listed below
Sorting:
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆38Updated last year
- Awesome machine learning for logic synthesis☆29Updated 3 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- ☆20Updated 3 years ago
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆28Updated 5 years ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆54Updated 10 months ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 7 months ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆20Updated 10 months ago
- Research paper based on or related to ABC.☆59Updated last week
- DATC RDF☆50Updated 5 years ago
- ☆16Updated 2 years ago
- Simple Python interface for ABC☆25Updated 2 years ago
- GPU-based logic synthesis tool☆93Updated this week
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆136Updated 3 months ago
- Collection of digital hardware modules & projects (benchmarks)☆69Updated last week
- A logic synthesis tool☆82Updated 2 months ago
- ☆18Updated 4 years ago
- ☆31Updated last year
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆34Updated 5 months ago
- ☆27Updated last year
- DATC Robust Design Flow.☆36Updated 5 years ago
- ☆13Updated 2 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- EPFL logic synthesis benchmarks☆216Updated last month
- LLM Evaluation Benchmark on Hardware Formal Verification☆33Updated 7 months ago
- Logic optimization and technology mapping tool.☆19Updated 2 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆40Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 5 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆33Updated last year