lydiawunan / IronManLinks
IronMan+alpha: Graph Neural Network and Reinforcement Learning in High-Level Synthesis
☆26Updated 3 years ago
Alternatives and similar repositories for IronMan
Users that are interested in IronMan are comparing it to the libraries listed below
Sorting:
- Dataset for ML-guided Accelerator Design☆39Updated 11 months ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆21Updated last year
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆51Updated last year
- ☆31Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ☆16Updated 3 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆18Updated 3 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆85Updated 6 months ago
- GPU-based logic synthesis tool☆93Updated 3 months ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆54Updated 10 months ago
- ☆54Updated 5 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆44Updated last week
- This repository contains the code for this paper: Chiplet-Gym: An RL-based Optimization Framework for Chiplet-based AI Accelerator☆21Updated last year
- A toolchain for rapid design space exploration of chiplet architectures☆63Updated 3 months ago
- ☆27Updated last year
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- ☆18Updated 6 months ago
- ☆31Updated 3 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 5 months ago
- ☆20Updated 3 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- ACM TODAES Best Paper Award, 2022☆30Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆106Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 5 months ago
- ☆15Updated 2 years ago
- ☆63Updated 6 months ago
- DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)☆114Updated 2 years ago