DexWen / FFT_VerilogLinks
FFT implement by verilog_测试验证已通过
☆57Updated 8 years ago
Alternatives and similar repositories for FFT_Verilog
Users that are interested in FFT_Verilog are comparing it to the libraries listed below
Sorting:
- AXI总线连接器☆97Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 9 months ago
- ☆36Updated 9 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- APB to I2C☆41Updated 10 years ago
- Pipeline FFT Implementation in Verilog HDL☆117Updated 6 years ago
- 视频旋转(2019FPGA大赛)☆34Updated 5 years ago
- ☆64Updated 9 years ago
- verilog☆21Updated last year
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆18Updated last year
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- AXI DMA 32 / 64 bits☆114Updated 10 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- ☆70Updated 3 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- Radix-4 1024 point fft in verilog☆10Updated 5 years ago
- 这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆89Updated 7 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆54Updated last year
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆54Updated 3 years ago
- PCIE 5.0 Graduation project (Verification Team)☆72Updated last year
- AXI Interconnect☆49Updated 3 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- Cortex M0 based SoC☆73Updated 3 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆14Updated 2 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago