WISHBONE Interconnect
☆11Oct 1, 2017Updated 8 years ago
Alternatives and similar repositories for wb_conmax
Users that are interested in wb_conmax are comparing it to the libraries listed below
Sorting:
- USB 1.1 Device IP Core☆21Oct 1, 2017Updated 8 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 11 years ago
- USB 2.0 Device IP Core☆74Oct 1, 2017Updated 8 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- Wishbone interconnect utilities☆44Feb 23, 2026Updated 2 weeks ago
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Jul 22, 2020Updated 5 years ago
- vhdl related contents☆11Apr 27, 2020Updated 5 years ago
- ☆17Nov 25, 2017Updated 8 years ago
- OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verificati…☆13Mar 1, 2026Updated last week
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Mirror of the Universal Verification Methodology from sourceforge☆37Jan 21, 2015Updated 11 years ago
- SystemVerilog wrapper over the Verilog Programming Interface (VPI)☆13Jun 3, 2025Updated 9 months ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- OSVVM project simulation scripts. Scripts are tedious. These scripts simplify the steps to compile your project for simulation☆14Mar 1, 2026Updated last week
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆17Jan 28, 2022Updated 4 years ago
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU☆15Oct 18, 2014Updated 11 years ago
- A Sphinx domain providing VHDL language support.☆20Dec 18, 2023Updated 2 years ago
- A VHDL Core Library.☆18Mar 29, 2017Updated 8 years ago
- Multi-function, universal, fixed-point CORDIC☆15Feb 20, 2022Updated 4 years ago
- general-cores☆21Jul 16, 2025Updated 7 months ago
- Verification IP for UART protocol☆23Aug 3, 2020Updated 5 years ago
- FPGA纯逻辑实现modbus通信☆23Sep 5, 2022Updated 3 years ago
- A plain VHDL implementation of a small microprocessor fully compatible with the ISA of the well known PicoBlaze by Ken Chapman.☆22Jun 6, 2021Updated 4 years ago
- ☆12May 21, 2024Updated last year
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆24May 13, 2023Updated 2 years ago
- DDR3 function verification environment in UVM☆26Apr 1, 2018Updated 7 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Aug 20, 2022Updated 3 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆27Jul 11, 2024Updated last year
- VHDL related news.☆27Mar 2, 2026Updated last week
- ☆11May 31, 2016Updated 9 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆33Oct 31, 2021Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 6 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- SDRAM controller with multiple wishbone slave ports☆30Oct 26, 2018Updated 7 years ago