Alternatives and similar repositories for wb_conmax

Users that are interested in wb_conmax are comparing it to the libraries listed below

• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• abdelazeem201 / SoC-Implementation-of-OpenMSP430-Microcontroller
  The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…
  ☆15Updated 3 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆17Updated 4 years ago
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆15Updated 7 months ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆22Updated 5 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆29Updated last year
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated last week
• ZipCPU / wbsata
  Wishbone SATA Controller
  ☆19Updated 3 months ago
• r09g / iadc
  12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm
  ☆21Updated 2 years ago
• pulp-platform / axi_llc
  ☆29Updated 3 weeks ago
• muneebullashariff / pulpino_soc_uvm_testbench
  UVM testbench for verifying the Pulpino SoC
  ☆14Updated 5 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated last week
• muneebullashariff / uart_vip
  Verification IP for UART protocol
  ☆20Updated 5 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆34Updated 3 months ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆32Updated 4 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated 11 months ago
• pulp-platform / hier-icache
  ☆13Updated 6 months ago
• pulp-platform / apb
  APB Logic
  ☆19Updated 2 weeks ago
• paulscherrerinstitute / PsiIpPackage
  TCL framework to package Vivado IP-Cores
  ☆14Updated 3 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated last year
• wnew / hdl_library
  A library of verilog and vhdl modules
  ☆15Updated 6 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆36Updated last week
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆14Updated 5 years ago
• pulp-platform / axi2apb
  ☆21Updated 5 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆12Updated 4 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆18Updated 2 years ago