www-asics-ws / wb_conmaxLinks
WISHBONE Interconnect
☆11Updated 8 years ago
Alternatives and similar repositories for wb_conmax
Users that are interested in wb_conmax are comparing it to the libraries listed below
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆16Updated 3 years ago
- To design test bench of the APB protocol☆18Updated 4 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆20Updated 4 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 6 years ago
- Generic AXI master stub☆19Updated 11 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 11 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated last week
- Verification IP for UART protocol☆21Updated 5 years ago
- SystemVerilog Logger☆19Updated 2 months ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- ☆33Updated last month
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- APB Logic☆22Updated last month
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- Generate UVM testbench framework template files with Python 3☆26Updated 6 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- ☆22Updated 6 years ago
- ☆16Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- USB -> AXI Debug Bridge☆41Updated 4 years ago
- Direct Access Memory for MPSoC☆13Updated last week