Alternatives and similar repositories for ECG-signal-processing-using-ModelSim

Users that are interested in ECG-signal-processing-using-ModelSim are comparing it to the libraries listed below

• Akhil-Yada / Adaptive-Filter
  An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…
  ☆12Updated 6 years ago
• Verdvana / Async_FIFO
  位宽和深度可定制的异步FIFO
  ☆13Updated last year
• fengyulin1996 / Verilog-DSP
  FIR，FFT based on Verilog
  ☆13Updated 7 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆20Updated 5 years ago
• muneebullashariff / pulpino_soc_uvm_testbench
  UVM testbench for verifying the Pulpino SoC
  ☆13Updated 5 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• DeamonYang / FPGA_FFT
  基于FPGA的FFT
  ☆17Updated 6 years ago
• sunzhengyuan / auto_simulate
  Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation
  ☆12Updated 5 years ago
• BAO-Rongxin / Intelligent-BLDC-driver
  The project includes codes, specification, presentation and other information.
  ☆26Updated 4 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• lulinchen / face_detect_open
  A Voila-Jones face detector hardware implementation
  ☆32Updated 6 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• DOUDIU / AXIS-AXI4-AXIS
  This project is designed to delay the output of the video stream in AXI-STREAM format.
  ☆11Updated 10 months ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆14Updated last year
• xycfwrj / zynq_axi_ddr_barebone
  minimal code to access ps DDR from PL
  ☆20Updated 5 years ago
• cam-n / human-detection-hog-svm
  A human detection system is developed on Matlab and FPGA: The 130x66 RGB pixels of static input image was attracted features and classifi…
  ☆11Updated 2 years ago
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆32Updated 4 years ago
• jimmyma8579 / FPGA_MotorControl
  PID controller with FPGA hardware
  ☆19Updated 5 years ago
• freecores / uart2spi
  UART To SPI
  ☆17Updated 10 years ago
• Elrori / OV_camera_on_FPGA
  OV7670 (Verilog HDL)Drive for FPGA
  ☆16Updated 6 years ago
• rbarzic / ml-ahb-gen
  A Verilog AMBA AHB Multilayer interconnect generator
  ☆12Updated 7 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆22Updated 6 years ago
• suisuisi / AXI4-Stream-FIR-filter
  AXI4-Stream FIR filter IP
  ☆17Updated 2 years ago
• edwardclin2003 / LowPassFilterImageFPGA
  Verilog code that does 2D Low Pass Filter on a greyscale image
  ☆10Updated 9 years ago
• srimanthtenneti / SOC-Design-ARM-M0
  This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.
  ☆11Updated last year
• Angelic47 / GowinDDR3_AXI4_SpinalHDL
  Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现
  ☆24Updated last year
• pulp-platform / pulp-builder
  ☆10Updated 5 years ago
• DeamonYang / FPGA_SDR
  软件无线电，使用FPGA进行正交解调。
  ☆22Updated 6 years ago
• cterrill26 / FPGA_AudioVisualizer
  Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…
  ☆15Updated 4 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆45Updated last month