hibagus / 64pointFFTProcessorLinks
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
☆34Updated 5 years ago
Alternatives and similar repositories for 64pointFFTProcessor
Users that are interested in 64pointFFTProcessor are comparing it to the libraries listed below
Sorting:
- Implementing Different Adder Structures in Verilog☆76Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- A 2D convolution hardware implementation written in Verilog☆51Updated 5 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆98Updated 6 years ago
- A verilog implementation for Network-on-Chip☆79Updated 7 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆54Updated 8 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- ☆74Updated 10 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆68Updated 9 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆76Updated 2 months ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 5 years ago
- BlackParrot on Zynq☆47Updated 3 weeks ago
- ☆54Updated 6 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆73Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆97Updated last year
- round robin arbiter☆77Updated 11 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆61Updated 2 years ago
- Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …☆31Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- ☆47Updated last year