Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
☆35May 20, 2020Updated 6 years ago
Alternatives and similar repositories for 64pointFFTProcessor
Users that are interested in 64pointFFTProcessor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Turbo coder and decoder☆12Oct 11, 2023Updated 2 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Radix-4 1024 point fft in verilog☆12Apr 29, 2020Updated 6 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆77Mar 16, 2026Updated 4 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Verilog code for a circuit implementation of Radix-2 FFT☆28Dec 5, 2021Updated 4 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 12 years ago
- Pure FPGA implementation of music spectrum and waveform display, supporting background image loading from an SD card,FIR filtering-based …☆32Jan 24, 2025Updated last year
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- TCP/IP and UDP/IP protocol stack off-loading☆19Aug 9, 2020Updated 6 years ago
- Nuclei AI Library Optimized For RISC-V Vector☆15Oct 15, 2025Updated 9 months ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆64Jun 30, 2026Updated last month
- Reference implementation of GFDM framework☆16Jun 14, 2018Updated 8 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆44Jun 6, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 5 years ago
- FFT implement by verilog_测试验证已通过☆62Sep 14, 2016Updated 9 years ago
- Generalized Frequency Division Multiplexing (GFDM) library for MATLAB.☆17Jun 27, 2018Updated 8 years ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 5 years ago
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆29Feb 18, 2021Updated 5 years ago
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- CUDA optimized Path Tracer☆10Dec 23, 2018Updated 7 years ago
- IEEE Executive project for the year 2021-2022☆12Nov 22, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆10Aug 22, 2023Updated 2 years ago
- Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware☆13Aug 24, 2020Updated 5 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Jun 5, 2020Updated 6 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆19Jul 21, 2020Updated 6 years ago
- FIR implemention with Verilog☆50May 18, 2019Updated 7 years ago
- Osmocom DSP utility function library; mirrored from https://gitea.osmocom.org/sdr/libosmo-dsp☆14Jun 24, 2025Updated last year
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆32Feb 21, 2019Updated 7 years ago
- Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predict…☆15Oct 9, 2017Updated 8 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- 基于FPGA的FFT☆19Feb 18, 2019Updated 7 years ago
- Multi Layer Perceptron by Vivado HLS for Xilinx FPGA implementation☆12Dec 26, 2016Updated 9 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆16Jul 14, 2019Updated 7 years ago
- Simple Path Tracer on an FPGA☆34Aug 29, 2021Updated 4 years ago
- A pipelined brainfuck softcore in Verilog☆20Aug 5, 2014Updated 12 years ago
- Hardware-accelerated sorting algorithm☆16May 4, 2020Updated 6 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆27Aug 23, 2021Updated 4 years ago