hibagus / 64pointFFTProcessorLinks
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
☆30Updated 5 years ago
Alternatives and similar repositories for 64pointFFTProcessor
Users that are interested in 64pointFFTProcessor are comparing it to the libraries listed below
Sorting:
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 10 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆86Updated 6 years ago
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆54Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆64Updated 8 years ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆15Updated 3 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆55Updated 3 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆45Updated 3 years ago
- Verilog RTL Design☆40Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆70Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆63Updated 2 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆75Updated 7 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- ☆34Updated 6 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated last year
- FFT implementation using CORDIC algorithm written in Verilog.☆33Updated 6 years ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago