hibagus / 64pointFFTProcessor
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
☆29Updated 4 years ago
Alternatives and similar repositories for 64pointFFTProcessor:
Users that are interested in 64pointFFTProcessor are comparing it to the libraries listed below
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆61Updated 8 months ago
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- ☆28Updated last year
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆15Updated 3 years ago
- AXI Interconnect☆47Updated 3 years ago
- ☆50Updated 2 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Simple single-port AXI memory interface☆41Updated 10 months ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆54Updated last year
- round robin arbiter☆72Updated 10 years ago
- ☆31Updated 5 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆17Updated 6 years ago
- Design and UVM-TB of RISC -V Microprocessor☆17Updated 9 months ago
- ☆36Updated 9 years ago
- Asynchronous fifo in verilog☆33Updated 9 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆24Updated 8 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆51Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- Must-have verilog systemverilog modules☆33Updated 2 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago