hxfycy / 1024-point-fftView external linksLinks
Radix-4 1024 point fft in verilog
☆13Apr 29, 2020Updated 5 years ago
Alternatives and similar repositories for 1024-point-fft
Users that are interested in 1024-point-fft are comparing it to the libraries listed below
Sorting:
- Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predict…☆15Oct 9, 2017Updated 8 years ago
- 基于FPGA的FFT☆19Feb 18, 2019Updated 6 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆73Aug 17, 2024Updated last year
- Verilog code for a circuit implementation of Radix-2 FFT☆27Dec 5, 2021Updated 4 years ago
- Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.☆34May 20, 2020Updated 5 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions.…☆31Feb 9, 2018Updated 8 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- 关于CIC滤波器、ISOP补偿器、HB滤波器的相关Matlab仿真与FPGA工程☆14Dec 25, 2023Updated 2 years ago
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- verilog实现systolic array及配套IO☆12Dec 2, 2024Updated last year
- 基于玄铁openc906，搭建最小化SoC系统☆17Apr 7, 2025Updated 10 months ago
- WM8731 Audio CODEC using Verilog (DE2-115)☆10Jul 28, 2019Updated 6 years ago
- 在家接入教育网IPv6的教程☆12Apr 23, 2021Updated 4 years ago
- A LaTex tamplate specially for Sun-Yet Sun University (SYSU).☆13Jan 19, 2022Updated 4 years ago
- Training models with ternary quantized weights using PyTorch☆15Jun 12, 2019Updated 6 years ago
- High-level synthesis (HLS) implementation of Sparse Matrix Vector Multiplication☆18Feb 17, 2022Updated 4 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆61Jul 21, 2023Updated 2 years ago
- FFT implement by verilog_测试验证已通过☆61Sep 14, 2016Updated 9 years ago
- 16-Point FFT is developed in order to accurately model that of the MATLAB function. . The module successfully tested using verilog testbe…☆18May 27, 2016Updated 9 years ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆16Dec 23, 2025Updated last month
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 2 years ago
- ☆15Sep 27, 2022Updated 3 years ago
- ☆14Apr 24, 2023Updated 2 years ago
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- This project aims to implement a full SDRAM controller for Altera DE2-115 FPGA☆13Nov 24, 2014Updated 11 years ago
- R22SDF FFT VLSI/FPGA investigate and implementation☆16Apr 22, 2022Updated 3 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.☆15May 29, 2020Updated 5 years ago
- ☆16Feb 5, 2021Updated 5 years ago
- Verilog module for calculation of FFT.☆192Aug 22, 2012Updated 13 years ago
- The code written on the understanding of the paper: "Manifold Regularization: A Geometric Framework for Learning from Labeled and Unlabel…☆18Apr 2, 2018Updated 7 years ago
- DDR3 SDRAM controller☆18Jul 17, 2014Updated 11 years ago
- An up5k board to manage pulse-echo ultrasound acquisition.☆28Jul 16, 2024Updated last year
- R2FFT is a fully synthesizable verilog module for doing the FFT on an FPGA or ASIC.☆22Apr 30, 2019Updated 6 years ago
- Educational 16-bit MIPS Processor☆18Feb 16, 2019Updated 7 years ago
- ☆25Oct 21, 2022Updated 3 years ago
- MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.☆25Oct 3, 2018Updated 7 years ago