Alternatives and similar repositories for hdmi-ts

Users that are interested in hdmi-ts are comparing it to the libraries listed below

• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆15Updated 5 months ago
• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆18Updated 10 months ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• FDU-ME-ARC / NVMeCHA
  ☆18Updated 3 years ago
• antmicro / openssd-nvme
  ☆25Updated 4 years ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 7 years ago
• kumarrishav14 / arm_watchdog
  Verification IP for Watchdog
  ☆11Updated 4 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆22Updated 7 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• zhouzaixin / arm_soc
  ☆14Updated 5 years ago
• Elphel / x393_sata
  mirror of https://git.elphel.com/Elphel/x393_sata
  ☆34Updated 5 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆15Updated 5 months ago
• alexforencich / verilog-ft245
  Verilog FT245 to AXI stream interface
  ☆29Updated 7 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• corundum / verilog-pcie
  Verilog PCI express components
  ☆22Updated 2 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆22Updated 7 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• hellgate202 / crc_calc
  Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
  ☆14Updated 6 years ago
• FarisHijazi / LZ4-Decompressor-Verilog
  Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language
  ☆16Updated 6 years ago
• FeldmeierMichael / MIPI_CSI_2
  ☆14Updated last year
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆13Updated 8 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆33Updated 4 months ago
• linuxbest / ahci_mpi
  an sata controller using smallest resource.
  ☆16Updated 11 years ago