Alternatives and similar repositories for 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm:

Users that are interested in 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm are comparing it to the libraries listed below

• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆56Updated 5 months ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆92Updated 5 years ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆39Updated last year
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆53Updated 2 years ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆20Updated 3 years ago
• Vidhi24-hub / 100daysofrtl
  ☆16Updated 9 months ago
• pareddy113 / Design-of-various-multiplier-Array-Booth-Wallace-
  ☆19Updated last year
• xupgit / Advanced-Embedded-System-Design-Flow-on-Zynq
  ☆52Updated 5 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆65Updated last year
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆25Updated 5 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆52Updated 8 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆85Updated 4 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• kuladeepsaireddy / OpenNoc
  ☆26Updated 5 years ago
• shubhi704 / APB-Protocol
  ☆38Updated 3 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆31Updated 8 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆77Updated 5 years ago
• abdelazeem201 / Introduction-to-System-on-Chip-Design-Online-Course
  To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA pla…
  ☆22Updated 4 years ago
• keyonhome / AXI4_LiteIP
  A verilog FPGA Interface for AXI4_Lite from Slave side
  ☆11Updated 4 years ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆16Updated last year
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆53Updated 9 months ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆88Updated 4 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆25Updated 3 years ago
• gokulbalagopal / Verification-of-FIFO-using-SystemVerilog
  Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…
  ☆25Updated 5 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆42Updated 4 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆71Updated 6 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆21Updated last year
• chengquan / IC_FLOW
  ☆14Updated last year
• djtfoo / lenet5-verilog
  A Verilog design of LeNet-5, a Convolutional Neural Network architecture
  ☆23Updated 4 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆30Updated 2 years ago