lucasbrasilino / net2axis
Verilog network module. Models network traffic from pcap to AXI-Stream
☆23Updated 3 years ago
Alternatives and similar repositories for net2axis:
Users that are interested in net2axis are comparing it to the libraries listed below
- Open source FPGA-based NIC and platform for in-network compute☆60Updated 2 months ago
- Ethernet switch implementation written in Verilog☆43Updated last year
- Groundhog - Serial ATA Host Bus Adapter☆21Updated 6 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- Hardware Assisted IEEE 1588 IP Core☆24Updated 10 years ago
- ☆16Updated 3 years ago
- Ethernet interface modules for Cocotb☆59Updated last year
- Verilog PCI express components☆21Updated last year
- Verilog Content Addressable Memory Module☆101Updated 2 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆43Updated last year
- This repo contains the Limago code☆79Updated 2 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆39Updated last year
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆43Updated 10 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Simple hash table on Verilog (SystemVerilog)☆48Updated 8 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- ☆22Updated 3 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆33Updated last year
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆61Updated 8 years ago
- ☆50Updated 3 years ago
- ☆45Updated 5 years ago
- Extensible FPGA control platform☆56Updated last year
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆36Updated 8 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 4 years ago
- PCI Express controller model☆47Updated 2 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆27Updated 2 years ago
- Framework for FPGA-accelerated Middlebox Development☆43Updated last year
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆14Updated 5 years ago
- Verilog Ethernet components for FPGA implementation☆18Updated last year