UVM verification platform for DW_apb_i2c IP core(Master Mode)
☆11Aug 21, 2023Updated 2 years ago
Alternatives and similar repositories for I2C
Users that are interested in I2C are comparing it to the libraries listed below
Sorting:
- ☆11May 8, 2022Updated 3 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 4 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- ☆18Jul 3, 2025Updated 8 months ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆40Jun 24, 2020Updated 5 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆17Oct 5, 2023Updated 2 years ago
- ☆19Aug 11, 2022Updated 3 years ago
- ☆25May 31, 2021Updated 4 years ago
- ☆18Aug 26, 2016Updated 9 years ago
- Verification IP for UART protocol☆23Aug 3, 2020Updated 5 years ago
- ☆21Feb 20, 2026Updated 2 weeks ago
- uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol☆21Feb 7, 2025Updated last year
- make your verilog DUT test more smart☆22Sep 9, 2016Updated 9 years ago
- a very simple risc_cpu verification demo with uvm☆26Apr 28, 2019Updated 6 years ago
- uvm_axi is a uvm package for modeling and verifying AXI protocol☆21Feb 7, 2025Updated last year
- Quad cluster of RISC-V cores with peripherals and local memory☆24Feb 3, 2022Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆76Mar 21, 2024Updated last year
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆31Jun 1, 2022Updated 3 years ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆42Jul 11, 2025Updated 7 months ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆30Mar 23, 2024Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆34Updated this week
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- 七路图像在FPGA中实现拼接，代码会不断添加进来。☆29Aug 17, 2021Updated 4 years ago
- Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functi…☆29Nov 21, 2020Updated 5 years ago
- 高通RaptorQ前向纠错码算法实现☆31Dec 9, 2025Updated 2 months ago
- A simple, scalable, source-synchronous, all-digital DDR link☆36Feb 24, 2026Updated last week
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- Simple template-based UVM code generator☆29Jan 4, 2023Updated 3 years ago
- ☆27May 11, 2021Updated 4 years ago
- This is for uvm_tb_gen☆52Feb 13, 2025Updated last year
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆25Jul 17, 2025Updated 7 months ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆31May 18, 2019Updated 6 years ago
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated 9 months ago
- This is the repository for the IEEE version of the book☆80Sep 29, 2020Updated 5 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago