Alternatives and similar repositories for I2C

Users that are interested in I2C are comparing it to the libraries listed below

• Nimausfi / UVM_RAL_DMA
  ☆11Updated 3 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆24Updated 5 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆17Updated 11 years ago
• marshall-999 / UVMReference
  This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).
  ☆13Updated 4 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆35Updated 2 years ago
• Anjali-287 / Synchronous-FIFO-UVM-TB
  UVM Testbench for synchronus fifo
  ☆17Updated 5 years ago
• JakodYuan / SVK-AMBA-VIP
  Simple AMBA VIP, Include axi/ahb/apb
  ☆27Updated last year
• Jon3Y / AMBA
  AHB/APB SRAM Inf, VCS&Verdi Sim.
  ☆14Updated 3 years ago
• Mohamed-Younis / SPI-UVM-Testbench
  ☆23Updated 4 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆19Updated 5 years ago
• deekshithkrishnegowda / AHB2APB-bridge-IP-core-verification
  Maven Silicon Project
  ☆19Updated 6 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆42Updated last year
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆26Updated 3 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• kumarswamy12 / ROUTER-1-3
  verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL
  ☆13Updated 6 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆69Updated 4 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆41Updated 3 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆37Updated 10 years ago
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆20Updated 12 years ago
• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆23Updated 3 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆37Updated 5 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆26Updated 7 months ago
• forever-gk / AHB-SystemVerilog
  ☆17Updated 10 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆52Updated 4 years ago
• DawnCarol / OpenC910_Modified
  commit rtl and build cosim env
  ☆15Updated last year
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆64Updated last year
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago