maxs-well / Ethernet-design-verilog
Gigabit Ethernet UDP communication driver
☆75Updated 5 years ago
Alternatives and similar repositories for Ethernet-design-verilog
Users that are interested in Ethernet-design-verilog are comparing it to the libraries listed below
Sorting:
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- FFT implement by verilog_测试验证已通过☆57Updated 8 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆92Updated 9 months ago
- Must-have verilog systemverilog modules☆34Updated 3 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆69Updated 3 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆53Updated 3 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆36Updated 8 years ago
- 视频旋转(2019FPGA大赛)☆33Updated 5 years ago
- 8b10b Encoder/Decoder☆11Updated 10 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆120Updated last year
- Verilog SPI master and slave☆53Updated 9 years ago
- ☆59Updated 2 years ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆176Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆70Updated last year
- ☆36Updated 9 years ago
- Ethernet MAC 10/100 Mbps☆81Updated 5 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- Cortex M0 based SoC☆73Updated 3 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。☆98Updated last year
- SPI Slave for FPGA in Verilog and VHDL