freecores / wdsp
DSP WishBone Compatible Cores
☆13Updated 10 years ago
Alternatives and similar repositories for wdsp:
Users that are interested in wdsp are comparing it to the libraries listed below
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆25Updated 3 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- ☆12Updated last month
- A CIC filter implemented in Verilog☆22Updated 9 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- FIR,FFT based on Verilog☆13Updated 7 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- ☆16Updated 5 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- USB 1.1 PHY☆10Updated 10 years ago
- APB Logic☆15Updated 3 months ago
- Generic AXI master stub☆19Updated 10 years ago
- PCI bridge☆18Updated 10 years ago
- double_fpu_verilog☆14Updated 10 years ago
- USB 1.1 Host and Function IP core☆21Updated 10 years ago
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆18Updated 7 years ago
- WISHBONE Builder☆14Updated 8 years ago
- Cortex-M0 DesignStart Wrapper☆18Updated 5 years ago
- USB Full Speed PHY☆42Updated 4 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆16Updated 2 years ago
- MMC (and derivative standards) host controller☆23Updated 4 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆11Updated last month
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆16Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year