freecores / wdspLinks
DSP WishBone Compatible Cores
☆14Updated 11 years ago
Alternatives and similar repositories for wdsp
Users that are interested in wdsp are comparing it to the libraries listed below
Sorting:
- Ethernet MAC 10/100 Mbps☆28Updated 4 years ago
- Generic AXI master stub☆19Updated 11 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- A CIC filter implemented in Verilog☆23Updated 10 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 4 years ago
- FIR,FFT based on Verilog☆13Updated 7 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆21Updated 2 years ago
- ☆16Updated 6 years ago
- ☆14Updated 7 years ago
- WISHBONE Interconnect☆11Updated 8 years ago
- USB 1.1 PHY☆11Updated 11 years ago
- AES☆14Updated 3 years ago
- DDR3 SDRAM controller☆18Updated 11 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆20Updated 8 months ago
- Cortex-M0 DesignStart Wrapper☆21Updated 6 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 6 years ago
- MMC (and derivative standards) host controller☆24Updated 5 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆18Updated 7 years ago
- ☆13Updated 2 years ago
- Verification IP for Watchdog☆11Updated 4 years ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- Xilinx IP repository☆13Updated 7 years ago
- Hardware Division Units☆10Updated 11 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- Verification of Ethernet Switch System Verilog☆11Updated 9 years ago