freecores / wdsp
DSP WishBone Compatible Cores
☆13Updated 10 years ago
Related projects ⓘ
Alternatives and complementary repositories for wdsp
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- FIR，FFT based on Verilog☆13Updated 6 years ago
- ☆11Updated 8 months ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆24Updated 3 years ago
- A CIC filter implemented in Verilog☆21Updated 9 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 3 years ago
- USB 1.1 Host and Function IP core☆19Updated 10 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Cortex-M0 DesignStart Wrapper☆17Updated 5 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆15Updated last year
- WISHBONE Builder☆13Updated 8 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆14Updated 3 months ago
- APB Logic☆12Updated 9 months ago
- ☆16Updated 5 years ago
- PCI bridge☆16Updated 10 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆26Updated 9 years ago
- Generic AXI master stub☆19Updated 10 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆14Updated 2 years ago
- ULPI Link Wrapper (USB Phy Interface)☆24Updated 4 years ago
- Wishbone interconnect utilities☆37Updated 6 months ago
- SystemVerilog Logger☆16Updated 2 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆12Updated 3 years ago
- hdmi-ts Project☆13Updated 7 years ago
- Generic AHB master stub☆10Updated 10 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆15Updated last year