benreynwar / fft-dit-fpgaLinks
Verilog module for calculation of FFT.
☆178Updated 12 years ago
Alternatives and similar repositories for fft-dit-fpga
Users that are interested in fft-dit-fpga are comparing it to the libraries listed below
Sorting:
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆89Updated 6 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆152Updated 5 months ago
- Verilog based BCH encoder/decoder☆123Updated 2 years ago
- Pipeline FFT Implementation in Verilog HDL☆126Updated 6 years ago
- Verilog UART☆177Updated 12 years ago
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago
- Verilog digital signal processing components☆146Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆359Updated last year
- SPI Master for FPGA - VHDL and Verilog☆297Updated last year
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- SPI Slave for FPGA in Verilog and VHDL☆208Updated last year
- AXI Interface Nand Flash Controller (Sync mode)☆96Updated 11 months ago
- Gigabit Ethernet UDP communication driver☆79Updated 6 years ago
- SDRAM controller with AXI4 interface☆96Updated 5 years ago
- An implementation of the CORDIC algorithm in Verilog.☆98Updated 6 years ago
- Fixed Point Math Library for Verilog☆138Updated 11 years ago
- Verilog SPI master and slave☆57Updated 9 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆85Updated 5 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆128Updated 4 years ago
- I2C controller core☆47Updated 2 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆38Updated 4 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆72Updated 4 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- AXI DMA 32 / 64 bits☆116Updated 11 years ago
- A configurable C++ generator of pipelined Verilog FFT cores☆245Updated last year
- JPEG Encoder Verilog☆77Updated 2 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆273Updated 5 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆49Updated 6 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago