Alternatives and similar repositories for fft-dit-fpga

Users that are interested in fft-dit-fpga are comparing it to the libraries listed below

• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆158Updated 9 months ago
• analogdevicesinc / fpgahdl_xilinx
  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…
  ☆89Updated 7 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆58Updated 9 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆159Updated 3 years ago
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆127Updated 3 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆147Updated 6 years ago
• maxs-well / Ethernet-design-verilog
  Gigabit Ethernet UDP communication driver
  ☆80Updated 6 years ago
• cjhonlyone / NandFlashController
  AXI Interface Nand Flash Controller (Sync mode)
  ☆98Updated last year
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆216Updated last year
• jamieiles / uart
  Verilog UART
  ☆186Updated 12 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆313Updated 2 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆397Updated 2 months ago
• cebarnes / cordic
  An implementation of the CORDIC algorithm in Verilog.
  ☆105Updated 7 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆39Updated 4 years ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆144Updated 11 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆112Updated last year
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆77Updated 4 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• freecores / i2c
  I2C controller core
  ☆47Updated 2 years ago
• ZipCPU / dblclockfft
  A configurable C++ generator of pipelined Verilog FFT cores
  ☆251Updated last year
• csus-senior-design / i2c
  I2C Master and Slave
  ☆37Updated 10 years ago
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆144Updated 2 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆71Updated 3 weeks ago
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆53Updated 11 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆515Updated 9 months ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆351Updated 8 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆122Updated 11 years ago