benreynwar / fft-dit-fpga
Verilog module for calculation of FFT.
☆167Updated 12 years ago
Alternatives and similar repositories for fft-dit-fpga:
Users that are interested in fft-dit-fpga are comparing it to the libraries listed below
- Fully parametrizable combinatorial parallel LFSR/CRC module☆144Updated this week
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆88Updated 6 years ago
- Verilog digital signal processing components☆129Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆307Updated 10 months ago
- Pipeline FFT Implementation in Verilog HDL☆99Updated 5 years ago
- An implementation of the CORDIC algorithm in Verilog.☆87Updated 6 years ago
- FFT implement by verilog_测试验证已通过☆53Updated 8 years ago
- Fixed Point Math Library for Verilog☆124Updated 10 years ago
- SPI Master for FPGA - VHDL and Verilog☆270Updated last year
- SPI Slave for FPGA in Verilog and VHDL☆194Updated 9 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆420Updated 3 years ago
- Verilog UART☆449Updated this week
- A configurable C++ generator of pipelined Verilog FFT cores☆230Updated 10 months ago
- AXI interface modules for Cocotb☆237Updated last year
- RTL Verilog library for various DSP modules☆85Updated 3 years ago
- AHB3-Lite Interconnect☆84Updated 9 months ago
- Verilog based BCH encoder/decoder☆117Updated 2 years ago
- Vivado诸多IP,包括图像处理等☆193Updated 7 months ago
- Verilog UART☆141Updated 11 years ago
- Gigabit Ethernet UDP communication driver☆73Updated 5 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆116Updated 3 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆264Updated 4 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆88Updated 6 months ago
- WISHBONE SD Card Controller IP Core☆119Updated 2 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆226Updated 2 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆191Updated last year
- 这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆84Updated 7 years ago
- ☆129Updated 9 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆122Updated 4 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆31Updated 3 years ago