Alternatives and similar repositories for verilogtools:

Users that are interested in verilogtools are comparing it to the libraries listed below

• www-asics-ws / wb_conmax
  WISHBONE Interconnect
  ☆11Updated 7 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆14Updated 2 months ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• freecores / wdsp
  DSP WishBone Compatible Cores
  ☆13Updated 10 years ago
• hellgate202 / crc_calc
  Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
  ☆12Updated 5 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• open-dv / dma_axi
  ☆16Updated 5 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 5 months ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆13Updated last year
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆11Updated 4 years ago
• trivedidvijen / SPI-to-I2C-Protocol-Conversion-Using-Verilog
  SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.
  ☆9Updated 3 years ago
• rakeshgehalot / Ethernet_switch_verification
  Verification of Ethernet Switch System Verilog
  ☆11Updated 8 years ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 6 years ago
• pulp-platform / hier-icache
  ☆12Updated last month
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆18Updated 5 years ago
• jchengX / MAC_BFM
  wifi
  ☆11Updated 7 years ago
• pulp-platform / axi2apb
  ☆19Updated 5 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆15Updated 6 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆36Updated 3 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• pulp-platform / apb
  APB Logic
  ☆15Updated 3 months ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆25Updated 3 years ago
• obilaniu / MVU
  Neural Network accelerator powered by MVUs and RISC-V.
  ☆13Updated 8 months ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆20Updated 6 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆18Updated 2 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago