Python tools for processing Verilog files
☆10Dec 7, 2011Updated 14 years ago
Alternatives and similar repositories for verilogtools
Users that are interested in verilogtools are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆15Jul 16, 2026Updated 3 months ago
- ☆17Nov 11, 2015Updated 10 years ago
- FPGA implementation of a handwritten digit recognition system based on k-nearest-neighbors (k-NN) classifier algorithm.☆21Apr 3, 2018Updated 8 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- SystemVerilog code for image processing tasks like demosaicing☆11Jun 28, 2020Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆25May 8, 2020Updated 6 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- A pipelined brainfuck softcore in Verilog☆20Aug 5, 2014Updated 12 years ago
- ☆24Oct 5, 2026Updated last week
- Pinky (8-bit CPU) written in Verilog and an Assembler written in Python 3☆19Oct 14, 2018Updated 8 years ago
- Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1☆40Feb 18, 2024Updated 2 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆21Dec 8, 2012Updated 13 years ago
- The RIFFA development repository (development fork)☆10Jun 11, 2024Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Table to Wikidata Mapping Language☆27Feb 3, 2023Updated 3 years ago
- VGA Tutorial for DE1☆16Apr 21, 2015Updated 11 years ago
- FIR band-pass filter using Verilog HDL.☆14Sep 7, 2026Updated last month
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- A Mel-frequency cepstrum core in FPGA☆22Jun 30, 2021Updated 5 years ago
- Testbenches for HDL projects☆23Updated this week
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆13Jan 15, 2017Updated 9 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆14Sep 28, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SystemVerilog Logger☆19Apr 6, 2026Updated 6 months ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- MMC (and derivative standards) host controller☆26Sep 14, 2020Updated 6 years ago
- generate UVM testbench using python☆28Mar 24, 2018Updated 8 years ago
- Make Vim complete like a modern editor - does the right thing. Works with Ultisnips and neocomplete.☆20Apr 15, 2017Updated 9 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆21Nov 13, 2024Updated last year
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- ☆12Jan 19, 2022Updated 4 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- AXI support for Migen/MiSoC☆28Oct 1, 2026Updated 2 weeks ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- HDMI + GPU-pipeline + FFT☆15Mar 4, 2016Updated 10 years ago
- HWASim is a simulator for heterogeneous systems with CPUs and Hardware Accelerators (HWAs). It is released with the DASH memory scheduler…☆19Jan 11, 2016Updated 10 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 6 years ago
- ☆29Feb 5, 2020Updated 6 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆37Apr 15, 2020Updated 6 years ago