Verilog Model for W25Q128JVxIM Serial Flash Memory
☆18Jun 7, 2020Updated 6 years ago
Alternatives and similar repositories for w25q128jvxim_v_sim
Users that are interested in w25q128jvxim_v_sim are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This place provide different SRAM cells netlist to be simulated with HSpice tool in sub-20nm FinFET technologies.☆12Dec 31, 2020Updated 5 years ago
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆13Aug 12, 2020Updated 6 years ago
- Hyperdimensional computing in memory. Artifact from 'A Case Study of Processing-in-Memory in off-the-Shelf Systems' (USENIX ATC '21)☆10Dec 2, 2023Updated 2 years ago
- Various projects of SPI loader module for xilinx fpga☆34Jul 20, 2020Updated 6 years ago
- A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley☆15Nov 30, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆24Oct 21, 2026Updated 2 weeks ago
- (CVPR 2024)Official implementation of KDBTS: Boosting Self-Supervision for Single-View Scene Completion via Knowledge Distillation☆10Jan 20, 2026Updated 9 months ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 6 years ago
- A basic verilog driver for the TM1638 LED and key matrix chip☆20Dec 22, 2017Updated 8 years ago
- ☆17Dec 15, 2017Updated 8 years ago
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated last year
- A common API for interfacing with secure services☆17Updated this week
- MNIST Database of Handwritten Digits☆18Aug 13, 2016Updated 10 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Code of "Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures", TCAD 2020☆14Apr 1, 2021Updated 5 years ago
- Raspberry Pico powered Xilinx Virtual Cable - Xilinx JTAG Cable!☆10Jun 2, 2022Updated 4 years ago
- ☆18Jul 23, 2018Updated 8 years ago
- I2S transciever implemented in Verilog HDL☆34Oct 11, 2017Updated 9 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- 模式识别实验：BP神经网络的matlab实现（根据BP数学原理实现的代码）☆16Apr 30, 2017Updated 9 years ago
- ☆13Jun 4, 2020Updated 6 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Sep 24, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- Agent skills for A-share research with source citations and structured Chinese reports.☆18Updated this week
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆34Feb 6, 2020Updated 6 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- The code for ICCV 2023 paper, Adaptive Reordering Sampler with Neurally Guided MAGSAC☆24Nov 29, 2023Updated 2 years ago
- This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efables…☆12Dec 6, 2023Updated 2 years ago
- SPI core☆12Jul 17, 2014Updated 12 years ago
- The one-click installer for MSYS2☆11Sep 17, 2025Updated last year
- HDMI + GPU-pipeline + FFT☆16Mar 4, 2016Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Simple projects with the CYC1000 FPGA board☆11Apr 21, 2020Updated 6 years ago
- A small and simple rv32i core written in Verilog☆19Jul 29, 2022Updated 4 years ago
- A ZipCPU demonstration port for the icoboard☆19Oct 21, 2021Updated 5 years ago
- code and data for paper Joint Image and Depth Estimation with Mask-Based Lensless Cameras☆12Oct 4, 2020Updated 6 years ago
- FPGA mandelbrot accelerator via high speed/super speed USB☆14Apr 6, 2023Updated 3 years ago
- Language for simplifying parameterized RTL design☆13Apr 3, 2026Updated 7 months ago
- PNG encoder, implemented in VHDL☆24Mar 30, 2024Updated 2 years ago
Are these results useful?