lijiaxun-sgms / w25q128jvxim_v_simLinks
Verilog Model for W25Q128JVxIM Serial Flash Memory
☆16Updated 5 years ago
Alternatives and similar repositories for w25q128jvxim_v_sim
Users that are interested in w25q128jvxim_v_sim are comparing it to the libraries listed below
Sorting:
- AHB DMA 32 / 64 bits☆58Updated 11 years ago
- UART -> AXI Bridge☆69Updated 4 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Updated 6 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- AXI DMA 32 / 64 bits☆124Updated 11 years ago
- PCIE 5.0 Graduation project (Verification Team)☆97Updated 2 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆65Updated 2 years ago
- APB to I2C☆43Updated 11 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- DDR2 memory controller written in Verilog☆79Updated 13 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- AHB3-Lite Interconnect☆109Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆74Updated 3 years ago
- RTL Verilog library for various DSP modules☆94Updated 3 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Updated 11 months ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Updated 11 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Updated 3 years ago
- AXI Interconnect☆56Updated 4 years ago
- SPI interface connect to APB BUS with Verilog HDL☆39Updated 4 years ago
- round robin arbiter☆77Updated 11 years ago
- AXI4 and AXI4-Lite interface definitions☆101Updated 5 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆117Updated 8 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆59Updated 5 years ago
- Verification IP for APB protocol☆75Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆17Updated last month
- Asynchronous fifo in verilog☆38Updated 9 years ago
- AMBA bus generator including AXI, AHB, and APB☆119Updated 4 years ago