freecores / pipelined_fft_64
Pipelined FFT/IFFT 64 points processor
☆11Updated 10 years ago
Related projects ⓘ
Alternatives and complementary repositories for pipelined_fft_64
- NoC based MPSoC☆10Updated 10 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Reed Solomon Decoder (204,188)☆11Updated 10 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- CORDIC VLSI-IP for deep learning activation functions☆13Updated 5 years ago
- Generic AXI master stub☆19Updated 10 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆29Updated 3 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆23Updated 5 months ago
- Repository gathering basic modules for CDC purpose☆50Updated 4 years ago
- ☆18Updated 8 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆13Updated 4 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- The memory model was leveraged from micron.☆19Updated 6 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆10Updated 3 weeks ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆9Updated last year
- Python Tool for UVM Testbench Generation☆48Updated 6 months ago
- ☆22Updated 8 months ago
- ☆25Updated 4 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 7 years ago
- verification of simple axi-based cache☆17Updated 5 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated last month
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆41Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆13Updated 4 months ago