freecores / pipelined_fft_64Links
Pipelined FFT/IFFT 64 points processor
☆11Updated 11 years ago
Alternatives and similar repositories for pipelined_fft_64
Users that are interested in pipelined_fft_64 are comparing it to the libraries listed below
Sorting:
- Various low power labs using sky130☆13Updated 4 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- ☆29Updated 2 weeks ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year
- APB Logic☆19Updated last month
- ☆21Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- NoC based MPSoC☆11Updated 11 years ago
- ☆19Updated 11 years ago
- Generic AXI master stub☆19Updated 11 years ago
- ☆21Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- General Purpose AXI Direct Memory Access☆59Updated last year
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆31Updated 9 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 4 years ago
- Python Tool for UVM Testbench Generation☆54Updated last year
- To design test bench of the APB protocol☆17Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆27Updated last year
- A 32 point radix-2 FFT module written in Verilog☆23Updated 5 years ago
- double_fpu_verilog☆16Updated 11 years ago
- An example Python-based MDV testbench for apbi2c core☆30Updated last year
- SoC Based on ARM Cortex-M3☆33Updated 4 months ago