Alternatives and similar repositories for SoC-Design-DDR3-Controller:

Users that are interested in SoC-Design-DDR3-Controller are comparing it to the libraries listed below

• wanderingnail / AXI_DMA
  ☆19Updated 2 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 3 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆31Updated 2 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆29Updated last week
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆33Updated 8 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆60Updated 4 years ago
• Ghonimo / Formal-Verification-of-an-AHB2APB-Bridge
  Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…
  ☆15Updated last year
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆53Updated last year
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆21Updated 6 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆42Updated 11 months ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆16Updated 10 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆54Updated 10 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 11 months ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆24Updated 2 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆48Updated 2 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆38Updated 2 years ago
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆24Updated 7 years ago
• jessepalomera / 10G_EthernetMAC_SystemVerilog_OOP
  Final Project for my course in Advanced Verification with SystemVerilog OOP
  ☆21Updated 3 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆19Updated 2 months ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆33Updated 9 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• freecores / robust_axi2ahb
  Generic AXI to AHB bridge
  ☆16Updated 10 years ago
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 3 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆43Updated 5 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 8 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆57Updated 4 years ago