funannoka / SoC-Design-DDR3-ControllerLinks
DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
☆32Updated 7 years ago
Alternatives and similar repositories for SoC-Design-DDR3-Controller
Users that are interested in SoC-Design-DDR3-Controller are comparing it to the libraries listed below
Sorting:
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆39Updated 8 years ago
- ☆26Updated 4 years ago
- ☆20Updated 3 years ago
- AXI Interconnect☆56Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- ☆38Updated 10 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆23Updated 7 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆25Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Updated 5 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆38Updated 3 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- DDR3 function verification environment in UVM☆26Updated 7 years ago
- UART -> AXI Bridge☆69Updated 4 years ago
- SoC Based on ARM Cortex-M3☆37Updated 8 months ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- ☆23Updated 6 years ago
- The memory model was leveraged from micron.☆28Updated 7 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 13 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- ☆28Updated 6 months ago
- ☆31Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Updated 3 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆74Updated last year
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago