A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
☆52Jul 4, 2019Updated 7 years ago
Alternatives and similar repositories for A-Single-Path-Delay-32-Point-FFT-Processor
Users that are interested in A-Single-Path-Delay-32-Point-FFT-Processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆53Dec 3, 2023Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆77Mar 16, 2026Updated 7 months ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆153Dec 2, 2019Updated 6 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 12 years ago
- FFT implement by verilog_测试验证已通过☆62Sep 14, 2016Updated 10 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆65Jun 30, 2026Updated 3 months ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 11 years ago
- PyTorch implementation of "Cluster-GCN: An Efficient Algorithm for Training Deep and Large Graph Convolutional Networks"☆12Mar 25, 2023Updated 3 years ago
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆17Jan 4, 2020Updated 6 years ago
- Pipeline FFT Implementation in Verilog HDL☆177Apr 14, 2019Updated 7 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Formal Verification of RISC V IM Processor☆12Mar 27, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A Single-path Delay Feedback FFT Generator☆15Mar 20, 2024Updated 2 years ago
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆32Mar 4, 2023Updated 3 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 7 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆25Feb 9, 2020Updated 6 years ago
- Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…☆19Jul 10, 2020Updated 6 years ago
- Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGA (DATE-19)☆15Jan 29, 2021Updated 5 years ago
- RTL Verilog library for various DSP modules☆103Feb 17, 2022Updated 4 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆20Jan 28, 2022Updated 4 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Implementing a Pipelined FFT using Verilog (Learning Project)☆17Jul 1, 2024Updated 2 years ago
- IEEE 802.11 OFDM-based transceiver system☆49Dec 15, 2017Updated 8 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆28Jul 4, 2019Updated 7 years ago
- ☆31Aug 8, 2020Updated 6 years ago
- This repo is to collect the state-of-the-art GNN hardware acceleration paper☆55Jun 8, 2021Updated 5 years ago
- Code for new techniques of VLSI placement☆13Oct 11, 2013Updated 13 years ago
- Verilog module for calculation of FFT.☆197Aug 22, 2012Updated 14 years ago
- MAC system with IEEE754 compatibility☆14Nov 22, 2023Updated 2 years ago
- H.264/AVC Baseline Decoder☆16Jul 17, 2014Updated 12 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An implementation of the CORDIC algorithm in Verilog.☆113Nov 19, 2018Updated 7 years ago
- Super scalar Processor design☆21Sep 7, 2014Updated 12 years ago
- ☆12Jan 23, 2022Updated 4 years ago
- RISC-V instruction set extensions for SM4 block cipher☆22Mar 6, 2020Updated 6 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆47Sep 26, 2023Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆84Aug 3, 2023Updated 3 years ago
- ECG signals acquired using a sensor has a lot of noise due to lung sounds and EMG. The noise due to lung sounds, EMG can be removed by us…☆13Nov 8, 2019Updated 6 years ago