A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
☆53Jul 4, 2019Updated 7 years ago
Alternatives and similar repositories for A-Single-Path-Delay-32-Point-FFT-Processor
Users that are interested in A-Single-Path-Delay-32-Point-FFT-Processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆54Dec 3, 2023Updated 2 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆153Dec 2, 2019Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆77Mar 16, 2026Updated 7 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 12 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- FFT implement by verilog_测试验证已通过☆62Sep 14, 2016Updated 10 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 11 years ago
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆28Jul 4, 2019Updated 7 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆65Oct 17, 2026Updated 2 weeks ago
- Pipeline FFT Implementation in Verilog HDL☆179Apr 14, 2019Updated 7 years ago
- An end-to-end GCN inference accelerator written in HLS☆18Apr 5, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆17Jan 4, 2020Updated 6 years ago
- PyTorch implementation of "Cluster-GCN: An Efficient Algorithm for Training Deep and Large Graph Convolutional Networks"☆12Mar 25, 2023Updated 3 years ago
- Formal Verification of RISC V IM Processor☆12Mar 27, 2022Updated 4 years ago
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆32Mar 4, 2023Updated 3 years ago
- A hardware accelerator for General Matrix Multiply, developed in SystemC using ESP.☆21May 26, 2021Updated 5 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆25Feb 9, 2020Updated 6 years ago
- Detailed read disturbance (RowHammer and RowPress) characterization of six real HBM2 DRAM chips yielding 23 new observations and 8 new ta…☆12May 3, 2024Updated 2 years ago
- Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGA (DATE-19)☆15Jan 29, 2021Updated 5 years ago
- A Single-path Delay Feedback FFT Generator☆15Mar 20, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- demo on simple channel router☆13Jan 3, 2019Updated 7 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…☆20Jul 10, 2020Updated 6 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 7 years ago
- RTL Verilog library for various DSP modules☆103Feb 17, 2022Updated 4 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆42Oct 4, 2024Updated 2 years ago
- Super scalar Processor design☆21Sep 7, 2014Updated 12 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆20Jan 28, 2022Updated 4 years ago
- An implementation of the CORDIC algorithm in Verilog.☆113Nov 19, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 助记词碰撞器下载/私钥碰撞器下载☆11Mar 12, 2025Updated last year
- Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the …☆19Dec 29, 2016Updated 9 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆47Sep 26, 2023Updated 3 years ago
- Code for new techniques of VLSI placement☆13Oct 11, 2013Updated 13 years ago
- H.264/AVC Baseline Decoder☆16Jul 17, 2014Updated 12 years ago
- IEEE 802.11 OFDM-based transceiver system☆49Dec 15, 2017Updated 8 years ago
- Implementing a Pipelined FFT using Verilog (Learning Project)☆17Jul 1, 2024Updated 2 years ago