jasonlin316 / A-Single-Path-Delay-32-Point-FFT-ProcessorLinks
A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
☆48Updated 5 years ago
Alternatives and similar repositories for A-Single-Path-Delay-32-Point-FFT-Processor
Users that are interested in A-Single-Path-Delay-32-Point-FFT-Processor are comparing it to the libraries listed below
Sorting:
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 9 months ago
- FFT implementation using CORDIC algorithm written in Verilog.☆32Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆42Updated last year
- Pipeline FFT Implementation in Verilog HDL☆119Updated 6 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆54Updated last year
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- ☆22Updated last year
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- AXI Interconnect☆49Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆32Updated 3 years ago
- ☆36Updated 9 years ago
- AXI总线连接器☆97Updated 5 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- FFT generator using Chisel☆59Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- FFT implement by verilog_测试验证已通过☆57Updated 8 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- R22SDF FFT VLSI/FPGA investigate and implementation☆15Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆85Updated 6 years ago
- AHB DMA 32 / 64 bits☆55Updated 10 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- AXI DMA 32 / 64 bits☆114Updated 10 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆18Updated last year