A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
☆49Jul 4, 2019Updated 6 years ago
Alternatives and similar repositories for A-Single-Path-Delay-32-Point-FFT-Processor
Users that are interested in A-Single-Path-Delay-32-Point-FFT-Processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆49Dec 3, 2023Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆76Mar 16, 2026Updated last month
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆148Dec 2, 2019Updated 6 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆36Sep 6, 2018Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 11 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- FFT implement by verilog_测试验证已通过☆61Sep 14, 2016Updated 9 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 10 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Pipeline FFT Implementation in Verilog HDL☆167Apr 14, 2019Updated 7 years ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆16Jan 4, 2020Updated 6 years ago
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Vivado project for Xilinx Artix FPGA, used in logic analyzer☆14Jul 16, 2021Updated 4 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 6 years ago
- A Single-path Delay Feedback FFT Generator☆14Mar 20, 2024Updated 2 years ago
- 使用verilog实现流水线 FFT☆15Jul 1, 2024Updated last year
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆25Feb 9, 2020Updated 6 years ago
- RTL Verilog library for various DSP modules☆96Feb 17, 2022Updated 4 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…☆19Jul 10, 2020Updated 5 years ago
- ULPI Link Wrapper (USB Phy Interface)☆37May 3, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Code for new techniques of VLSI placement☆13Oct 11, 2013Updated 12 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- IEEE 802.11 OFDM-based transceiver system☆44Dec 15, 2017Updated 8 years ago
- This repo is to collect the state-of-the-art GNN hardware acceleration paper☆55Jun 8, 2021Updated 4 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Aug 18, 2022Updated 3 years ago
- An implementation of the CORDIC algorithm in Verilog.☆109Nov 19, 2018Updated 7 years ago
- ☆13Jan 23, 2022Updated 4 years ago
- Hardware and software implementation of Sparsely-active SNNs☆22Mar 6, 2026Updated 2 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆84Aug 3, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆17Feb 13, 2021Updated 5 years ago
- RISC-V instruction set extensions for SM4 block cipher☆21Mar 6, 2020Updated 6 years ago
- A small Neural Network Processor for Edge devices.☆19Nov 22, 2022Updated 3 years ago
- Matrix Multiplication in Hardware☆16Jun 3, 2020Updated 5 years ago
- Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the …☆19Dec 29, 2016Updated 9 years ago
- ECG signals acquired using a sensor has a lot of noise due to lung sounds and EMG. The noise due to lung sounds, EMG can be removed by us…☆13Nov 8, 2019Updated 6 years ago
- A CIC filter implemented in Verilog☆24Sep 7, 2015Updated 10 years ago