Alternatives and similar repositories for WM8731-Audio-CODEC

Users that are interested in WM8731-Audio-CODEC are comparing it to the libraries listed below

• nour176yj / FIR-LPF-Digital-Design-
  A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ
  ☆14Updated 2 years ago
• vipinkmenon / ZynqOLED
  Source code for Zynq OLED controller
  ☆15Updated 5 years ago
• MostafaOkasha / ECHO-and-FIR-FILTER-implementation-on-Verilog-HDL
  Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…
  ☆10Updated 6 years ago
• Reenforcements / VerilogDE2115AudioFilters
  Student project for using audio on the DE2-115 FPGA development board.
  ☆27Updated 7 years ago
• chenshuo / veriloglabs
  Undergraduate digital circuit laboratory
  ☆29Updated 2 years ago
• Verdvana / OV5640_SDRAM
  OV5640摄像头驱动及TFT屏幕显示
  ☆16Updated 6 years ago
• sujan2599 / LMS-Adaptive-FIR-Filter
  design of LMS adaptive 4-tap FIR filter using Distributed Arithmetic architecture in verilog
  ☆10Updated 3 years ago
• Digilent / Zedboard-DMA
  ☆13Updated 6 years ago
• suisuisi / AXI4-Stream-FIR-filter
  AXI4-Stream FIR filter IP
  ☆19Updated 3 years ago
• maxs-well / FIR_Implementation
  FIR filter implementation
  ☆29Updated 5 years ago
• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆51Updated 5 years ago
• donpromax / ECC-Verilog-HDL-AutoGenerator
  a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.
  ☆11Updated 6 years ago
• vipinkmenon / SpatialFilter
  ☆63Updated last year
• BIGWJZ / VLSI-DSP-Review
  ☆76Updated 5 years ago
• Basantloay / Softmax_CNN
  This repository contains full code of Softmax Layer in Verilog
  ☆20Updated 5 years ago
• Danishazmi29 / Verilog-Code-of-Synchronus-FIFO-Design-with-verilog-test-code
  A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…
  ☆16Updated 8 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆69Updated last year
• AngeloJacobo / FPGA_RealTime_and_Static_Sobel_Edge_Detection
  Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
  ☆66Updated 4 years ago
• ShichenQiao / ECE554_SP23_FPGA_Handwriting_Recognition
  Senior Design Project at UW-Madison ECE
  ☆19Updated 2 years ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆17Updated 2 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆68Updated 3 years ago
• Springbone / CC-Cam
  CC-Cam: A diffuser camera based on Pynq-Z2
  ☆20Updated 5 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• Aperture-Electronic / Realtime-Bicubic-16X-SuperResolution-IP
  APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS
  ☆28Updated 2 years ago
• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆36Updated 3 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆58Updated 11 years ago
• Xilinx / xup_embedded_system_design_flow
  AMD Xilinx University Program Embedded tutorial
  ☆43Updated 2 years ago
• sandy2008 / CNN-FPGA
  ☆19Updated 7 years ago
• bol-edu / caravel-soc_fpga-lab
  ☆20Updated 9 months ago
• basemhesham / Design-and-ASIC-Implementation-of-UART
  This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…
  ☆25Updated last year