VenciFreeman / FFT_ChipDesignLinks
A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
☆69Updated last year
Alternatives and similar repositories for FFT_ChipDesign
Users that are interested in FFT_ChipDesign are comparing it to the libraries listed below
Sorting:
- AXI DMA 32 / 64 bits☆123Updated 11 years ago
- ☆68Updated 3 years ago
- A verilog implementation for Network-on-Chip☆80Updated 7 years ago
- ☆40Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆114Updated 5 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- AXI总线连接器☆105Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- FFT implement by verilog_测试验证已通过☆60Updated 9 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- AHB DMA 32 / 64 bits☆57Updated 11 years ago
- ☆74Updated 10 years ago
- An AXI4 crossbar implementation in SystemVerilog☆203Updated 4 months ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- FFT generator using Chisel☆62Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆41Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆98Updated 6 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆61Updated 2 years ago
- PCIE 5.0 Graduation project (Verification Team)☆97Updated last year
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆50Updated 6 years ago
- AXI Interconnect☆54Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆118Updated 4 years ago
- 3×3脉动阵列乘法器☆50Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- Pipeline FFT Implementation in Verilog HDL☆155Updated 6 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated last month