FFT implementation using CORDIC algorithm written in Verilog.
☆36Sep 6, 2018Updated 7 years ago
Alternatives and similar repositories for FFT-cordic-HDL
Users that are interested in FFT-cordic-HDL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- High Radix Adaptive CORDIC Algorithm - Improvement over Traditional CORDIC☆14Jul 15, 2016Updated 9 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 6 years ago
- FFT implement by verilog_测试验证已通过☆61Sep 14, 2016Updated 9 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- configurable cordic core in verilog☆54Jul 17, 2014Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆78Mar 16, 2026Updated 2 months ago
- Pipeline FFT Implementation in Verilog HDL☆167Apr 14, 2019Updated 7 years ago
- The CORDIC algorithm implemented in Octave/MATLAB and Verilog☆32Mar 31, 2015Updated 11 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆21Dec 8, 2012Updated 13 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆50Jul 4, 2019Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆49Dec 3, 2023Updated 2 years ago
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆62Jul 5, 2022Updated 3 years ago
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆29Mar 26, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Chisel implementation of Neural Processing Unit for System on the Chip☆32May 22, 2026Updated last week
- Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.☆35May 20, 2020Updated 6 years ago
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆19Jul 24, 2021Updated 4 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- 2024年全国大学生电子设计大赛省赛B题参赛设计☆14Sep 17, 2024Updated last year
- ☆14Feb 24, 2025Updated last year
- ☆14Nov 11, 2015Updated 10 years ago
- hardware implement of huffman coding(written in verilog)☆14Jul 30, 2017Updated 8 years ago
- IEEE 802.11 OFDM-based transceiver system☆45Dec 15, 2017Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- safe, no-cost and easy-to-use Cpp header to work safely with HW registers☆14Sep 15, 2024Updated last year
- L1 Data, L1 Instruction and L2 Unified Cache Design☆16Updated this week
- A pipelined cordic algoithm for computing cos(angle) and sin(angle) in verilog☆19May 29, 2017Updated 9 years ago
- Verilog code for a circuit implementation of Radix-2 FFT☆28Dec 5, 2021Updated 4 years ago
- Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the …☆19Dec 29, 2016Updated 9 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Updated this week
- QSPI for SoC☆23Nov 8, 2019Updated 6 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆78Dec 7, 2020Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- C++ static vector class template. Also might be known as fixed vector or on-stack vector.☆13Jul 8, 2022Updated 3 years ago
- Verilog module for calculation of FFT.☆193Aug 22, 2012Updated 13 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 6 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆28Jul 17, 2025Updated 10 months ago
- Wishbone controlled I2C controllers☆57Nov 12, 2024Updated last year
- SPI interface connect to APB BUS with Verilog HDL☆42Jun 27, 2021Updated 4 years ago