FFT implementation using CORDIC algorithm written in Verilog.
☆36Sep 6, 2018Updated 7 years ago
Alternatives and similar repositories for FFT-cordic-HDL
Users that are interested in FFT-cordic-HDL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- High Radix Adaptive CORDIC Algorithm - Improvement over Traditional CORDIC☆14Jul 15, 2016Updated 10 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 7 years ago
- FFT implement by verilog_测试验证已通过☆62Sep 14, 2016Updated 9 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- configurable cordic core in verilog☆54Jul 17, 2014Updated 12 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Pipeline FFT Implementation in Verilog HDL☆170Apr 14, 2019Updated 7 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆78Mar 16, 2026Updated 4 months ago
- The CORDIC algorithm implemented in Octave/MATLAB and Verilog☆32Mar 31, 2015Updated 11 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆21Dec 8, 2012Updated 13 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆50Jul 4, 2019Updated 7 years ago
- 2024年全国大学生电子设计大赛省赛B题参赛设计☆14Sep 17, 2024Updated last year
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- HDLBits-Solutions☆12May 27, 2022Updated 4 years ago
- Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.☆35May 20, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆32Mar 26, 2017Updated 9 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- hardware implement of huffman coding(written in verilog)☆14Jul 30, 2017Updated 9 years ago
- VGA LCD Core (OpenCores)☆15May 22, 2018Updated 8 years ago
- IEEE 802.11 OFDM-based transceiver system☆49Dec 15, 2017Updated 8 years ago
- ☆14Jul 16, 2026Updated 2 weeks ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆34May 22, 2026Updated 2 months ago
- A pipelined cordic algoithm for computing cos(angle) and sin(angle) in verilog☆19May 29, 2017Updated 9 years ago
- Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the …☆19Dec 29, 2016Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆15Nov 11, 2015Updated 10 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Updated this week
- QSPI for SoC☆23Nov 8, 2019Updated 6 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design☆16May 26, 2026Updated 2 months ago
- SPI interface connect to APB BUS with Verilog HDL☆43Jun 27, 2021Updated 5 years ago
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- Wishbone controlled I2C controllers☆58Jul 15, 2026Updated 2 weeks ago
- Verilog module for calculation of FFT.☆196Aug 22, 2012Updated 13 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 6 years ago
- VEXTPROJ - the version control friendly system for creation of Vivado projects☆13Oct 25, 2025Updated 9 months ago
- A 2-demensional fast furior transform project for image processing.☆10Sep 4, 2020Updated 5 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- An implementation of the CORDIC algorithm in Verilog.☆111Nov 19, 2018Updated 7 years ago
- demo code for "Principles on Learning New Features for Effective Dense Matching"☆12Nov 1, 2016Updated 9 years ago
- Pre-trained models of MC-CNN in Chainer☆14Nov 14, 2018Updated 7 years ago