akhan3 / async-fifoLinks
Asynchronous FIFO for transferring data between two asynchronous clock domains
☆17Updated 9 years ago
Alternatives and similar repositories for async-fifo
Users that are interested in async-fifo are comparing it to the libraries listed below
Sorting:
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- ☆20Updated 2 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆58Updated last year
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- FPGA 同步FIFO与异步FIFO☆31Updated 6 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆59Updated 5 years ago
- UART -> AXI Bridge☆61Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆39Updated 5 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆11Updated 3 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- A simple, scalable, source-synchronous, all-digital DDR link☆27Updated 3 weeks ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆17Updated 5 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- ☆69Updated 3 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆18Updated 6 years ago
- few python scripts to clone all IP cores from opencores.org☆24Updated last year
- ☆28Updated 3 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- Implementation of the PCIe physical layer☆45Updated this week
- 10G Low Latency Ethernet☆56Updated 2 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆68Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- APB master and slave developed in RTL.☆17Updated 3 months ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆21Updated 7 years ago