kaitoukito / YSYX-NJU-GroupView external linksLinks
YSYX RISC-V Project NJU Study Group
☆16Jan 3, 2025Updated last year
Alternatives and similar repositories for YSYX-NJU-Group
Users that are interested in YSYX-NJU-Group are comparing it to the libraries listed below
Sorting:
- 一生一芯CPU/目前做到cache/后续主要考虑ASIC DV☆22Jan 13, 2025Updated last year
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- WISHBONE Builder☆15Sep 10, 2016Updated 9 years ago
- ☆72Apr 23, 2023Updated 2 years ago
- Verification IP for SPI protocol☆20Jul 23, 2020Updated 5 years ago
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated last month
- AXI Interconnect☆57Aug 20, 2021Updated 4 years ago
- ☆70Aug 30, 2022Updated 3 years ago
- This is the fork of CVA6 intended for PULP development.☆22Updated this week
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Aug 14, 2024Updated last year
- DDR3 function verification environment in UVM☆26Apr 1, 2018Updated 7 years ago
- RISCV CPU implementation in SystemVerilog☆32Oct 1, 2025Updated 4 months ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆75Mar 21, 2024Updated last year
- ☆11May 31, 2016Updated 9 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 6 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆76Nov 8, 2025Updated 3 months ago
- Contains commonly used UVM components (agents, environments and tests).☆32Aug 17, 2018Updated 7 years ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆34Jul 17, 2022Updated 3 years ago
- P4_16 reference compiler☆20Dec 30, 2025Updated last month
- MIPS 57条指令五级流水线cpu (verilog实现+详细注释)☆11Jan 11, 2022Updated 4 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆38Nov 24, 2022Updated 3 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆43Sep 26, 2023Updated 2 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆159May 10, 2025Updated 9 months ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆15Nov 24, 2025Updated 2 months ago
- FIR implemention with Verilog☆50May 18, 2019Updated 6 years ago
- Collect some IC textbooks for learning.☆183Aug 11, 2022Updated 3 years ago
- ☆92Sep 30, 2025Updated 4 months ago
- wifi☆12Jun 13, 2017Updated 8 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- ☆10Mar 19, 2025Updated 10 months ago
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆16Mar 3, 2018Updated 7 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆12Sep 3, 2019Updated 6 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago