YSYX RISC-V Project NJU Study Group
☆16Jan 3, 2025Updated last year
Alternatives and similar repositories for YSYX-NJU-Group
Users that are interested in YSYX-NJU-Group are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 一生一芯CPU/目前做到cache/后续主要考虑ASIC DV☆22Jan 13, 2025Updated last year
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- ☆79Apr 23, 2023Updated 3 years ago
- WISHBONE Builder☆15Sep 10, 2016Updated 9 years ago
- Parallel_Computer_Architecture经典书籍☆17May 13, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- MIPS 57条指令五级流水线cpu (verilog实现+详细注释)☆11Jan 11, 2022Updated 4 years ago
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Apr 6, 2023Updated 3 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 5 years ago
- ☆13Mar 19, 2025Updated last year
- This is the fork of CVA6 intended for PULP development.☆23Jun 29, 2026Updated last week
- ☆95Apr 14, 2026Updated 2 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆21Dec 1, 2023Updated 2 years ago
- P4_16 reference compiler☆23Dec 30, 2025Updated 6 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 6 months ago
- Simple test of ARM NEON code. Performs a blit to the framebuffer.☆15Jul 23, 2013Updated 12 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- AXI Interconnect☆57Aug 20, 2021Updated 4 years ago
- Collect some IC specs for learning.☆24Jun 25, 2024Updated 2 years ago
- 我的一生一芯项目☆16Dec 14, 2021Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆173May 10, 2025Updated last year
- RISCV CPU implementation in SystemVerilog☆32Jun 7, 2026Updated last month
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A convolution based 3x3 GaussianBlur implementation using ARM NEON assembly engine☆10Jan 20, 2019Updated 7 years ago
- 操作系统经典书籍☆24May 13, 2022Updated 4 years ago
- ☆77Aug 30, 2022Updated 3 years ago
- Tensor Processing Unit implementation in Verilog☆14Mar 18, 2025Updated last year
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 5 years ago
- ☆24Jun 12, 2026Updated 3 weeks ago
- 上海大学 课程实验报告LaTex模板☆17Mar 23, 2023Updated 3 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆17Apr 17, 2021Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆45Sep 26, 2023Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.☆37Jun 25, 2026Updated 2 weeks ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- ☆10Jan 30, 2017Updated 9 years ago
- ☆13May 8, 2025Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆86Mar 21, 2024Updated 2 years ago
- 简单易用的微信小程序倒计时库☆15May 15, 2018Updated 8 years ago