Lumen-Laboratory / MayoiutaView external linksLinks
Open-source Neural Processing Unit (NPU) from China ❤
☆35Jan 29, 2025Updated last year
Alternatives and similar repositories for Mayoiuta
Users that are interested in Mayoiuta are comparing it to the libraries listed below
Sorting:
- A small Neural Network Processor for Edge devices.☆15Nov 22, 2022Updated 3 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 9 months ago
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆24Updated this week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Nov 1, 2025Updated 3 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- ☆11Jul 28, 2022Updated 3 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆33Feb 3, 2026Updated last week
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year
- Digital IC design and vlsi notes☆12Jun 24, 2020Updated 5 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆21Mar 25, 2025Updated 10 months ago
- ☆15May 13, 2025Updated 9 months ago
- SystemVerilog implemention of the TAGE branch predictor☆13May 26, 2021Updated 4 years ago
- ☆17Dec 21, 2020Updated 5 years ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 3 years ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Feb 4, 2026Updated last week
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- ☆21Sep 26, 2025Updated 4 months ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆33Oct 23, 2024Updated last year
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆13Dec 4, 2025Updated 2 months ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated 11 months ago
- Open NPU is an open-source project dedicated to creating a flexible, extensible, and high-performance neural processing unit (NPU) archit…☆17Jun 20, 2024Updated last year
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 10 months ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆24Mar 13, 2025Updated 11 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆46Jan 2, 2025Updated last year
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated 11 months ago
- Implementation of an NPU that can be integrated into a RISC- V core through X-Interface.☆34Sep 17, 2024Updated last year
- ☆18Jul 5, 2023Updated 2 years ago
- RISC-V IOMMU in verilog☆23Jun 18, 2022Updated 3 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆32Aug 13, 2024Updated last year
- A fork of Xiangshan for AI☆36Feb 6, 2026Updated last week
- ☆20Dec 19, 2025Updated last month
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated last year