Lumen-Laboratory / Mayoiuta
Open-source Neural Processing Unit (NPU) from China ❤
☆11Updated 2 months ago
Alternatives and similar repositories for Mayoiuta:
Users that are interested in Mayoiuta are comparing it to the libraries listed below
- ☆17Updated last week
- VSH(SHell for Visualizing vcd file)项目为数字波形文件命令行查看器。☆16Updated 3 weeks ago
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆18Updated 7 months ago
- 本项目已被合并至官方Chiplab中☆10Updated 2 months ago
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆15Updated 4 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- ☆24Updated 2 months ago
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆13Updated 2 months ago
- This is an IDE for YSYX_NPC debuging☆11Updated 3 months ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆11Updated 8 months ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆11Updated this week
- Unofficial guide for ysyx students applying to ShanghaiTech University☆21Updated last month
- 给NEMU移植Linux Kernel!☆14Updated last week
- Basic chisel difftest environment for RTL design (WIP☆18Updated 3 weeks ago
- A riscv emulator.☆19Updated last year
- ☆17Updated 7 months ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆16Updated 6 months ago
- SystemVerilog implemention of the TAGE branch predictor☆11Updated 3 years ago
- A Flexible Cache Architectural Simulator☆13Updated 3 months ago
- "aura" my super-scalar O3 cpu core☆24Updated 10 months ago
- ☆11Updated 9 months ago
- 开源软件通识课程 (Introduction to Open Source Software),本课程暂定设计面向信息大类专业的大一学生☆28Updated 3 weeks ago
- Build mini linux for your own RISC-V emulator!☆19Updated 6 months ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆16Updated 3 weeks ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆48Updated 4 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆30Updated 11 months ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆38Updated 8 months ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆10Updated 2 years ago
- ☆11Updated last month
- RISC-V 64 CPU☆10Updated 2 years ago