Alternatives and similar repositories for acceltran

Users that are interested in acceltran are comparing it to the libraries listed below

• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆52Updated 3 years ago
• hatsu3 / Sanger
  ☆49Updated 3 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆54Updated 3 months ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆32Updated this week
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆39Updated 2 years ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆60Updated 4 months ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆85Updated 3 years ago
• GATECH-EIC / ViTCoD
  [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design
  ☆108Updated 2 years ago
• albertomarchisio / SwiftTron
  ☆44Updated 2 years ago
• fffasttime / AnyPackingNet
  ☆27Updated 3 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆79Updated 3 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆54Updated last week
• abdelfattah-lab / BitMoD-HPCA-25
  ☆45Updated 7 months ago
• sjtu-zhao-lab / SALO
  An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences
  ☆29Updated last year
• isakedo / DNNsim
  ☆35Updated 5 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆45Updated 2 years ago
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆16Updated last year
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆54Updated 3 months ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆106Updated 5 years ago
• sunxt99 / PIMCOMP-NN
  ☆65Updated 5 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆80Updated 11 months ago
• mit-han-lab / spatten
  [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
  ☆94Updated 10 months ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆73Updated 5 months ago
• mit-emze / cimloop
  ☆61Updated last month
• KULeuven-MICAS / zigzag-llm
  Model LLM inference on single-core dataflow accelerators
  ☆10Updated 4 months ago
• sharc-lab / Edge-MoE
  Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts
  ☆122Updated last year
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆147Updated this week
• wangxy-2000 / pimsim-nn
  ☆52Updated last year
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆132Updated 5 months ago