jha-lab / acceltranLinks
[TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
☆54Updated 2 years ago
Alternatives and similar repositories for acceltran
Users that are interested in acceltran are comparing it to the libraries listed below
Sorting:
- Open-source of MSD framework☆16Updated 2 years ago
- ☆47Updated 4 years ago
- A co-design architecture on sparse attention☆54Updated 4 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆35Updated this week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆73Updated last month
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Updated 2 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆124Updated 2 years ago
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago
- ☆46Updated 2 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆116Updated last year
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated 2 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- Model LLM inference on single-core dataflow accelerators☆17Updated last week
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 2 months ago
- ☆35Updated 5 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆30Updated last year
- ☆51Updated 2 weeks ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- ☆58Updated last year
- ☆31Updated 8 months ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆78Updated 7 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆45Updated last year
- MICRO22 artifact evaluation for Sparseloop☆45Updated 3 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆129Updated last year
- ☆33Updated 2 weeks ago
- ☆75Updated last week
- ☆42Updated last year