Alternatives and similar repositories for SALO

Users that are interested in SALO are comparing it to the libraries listed below

• hatsu3 / Sanger
  ☆47Updated 4 years ago
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆54Updated 4 years ago
• CLab-HKUST-GZ / micro58-axcore
  ☆26Updated last month
• leesou / H2-LLM-ISCA-2025
  H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference
  ☆77Updated 7 months ago
• jeffreyyu0602 / quantized-training
  ☆32Updated this week
• GATECH-EIC / ViTALiTy
  ViTALiTy (HPCA'23) Code Repository
  ☆23Updated 2 years ago
• mit-han-lab / spatten
  [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
  ☆115Updated last year
• clevercool / ANT-Quantization
  ☆112Updated 2 years ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆54Updated 2 years ago
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆105Updated 7 months ago
• scalesim-project / scale-sim-v3
  ☆50Updated last week
• GATECH-EIC / ViTCoD
  [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design
  ☆124Updated 2 years ago
• SFU-HiAccel / HiSpMV
  [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS
  ☆17Updated 3 months ago
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆18Updated last year
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆71Updated last month
• SET-Scheduling-Project / SoMa-HPCA2025
  ☆25Updated 9 months ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆44Updated 3 years ago
• kelvin0207 / SparSynergy
  Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…
  ☆21Updated 8 months ago
• witmemtech / CIM-Technical-Papers-Collection
  Computing in memory optimizes data handling by performing operations directly in memory, ideal for high-speed data processing needs. This…
  ☆29Updated last year
• Zhaoshixin-sky / CIM-MLC
  [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators
  ☆45Updated last year
• snu-comparch / Tender
  Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)
  ☆23Updated last year
• scale-snu / attacc_simulator
  ☆113Updated last year
• fangjh21 / PALM
  PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training
  ☆19Updated last year
• mit-emze / cimloop
  ☆74Updated 2 months ago
• isakedo / DNNsim
  ☆35Updated 5 years ago
• casys-kaist / NeuPIMs
  NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing
  ☆104Updated last year
• SET-Scheduling-Project / SET-ISCA2023
  The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.
  ☆81Updated 8 months ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆42Updated 2 years ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆69Updated 2 months ago
• FPSG-UIUC / micro24-fusemax-artifact
  MICRO 2024 Evaluation Artifact for FuseMax
  ☆16Updated last year