Alternatives and similar repositories for Flute:

Users that are interested in Flute are comparing it to the libraries listed below

• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆28Updated this week
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆58Updated 3 weeks ago
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆32Updated 2 years ago
• ymanerka / pipeproof
  PipeProof
  ☆11Updated 5 years ago
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆18Updated 5 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆33Updated last month
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆41Updated 6 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆19Updated 6 years ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆35Updated 3 years ago
• Minres / DBT-RISE-RISCV
  An instruction set simulator based on DBT-RISE implementing the RISC-V ISA
  ☆35Updated 4 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆44Updated last year
• StanfordAHA / doc
  Papers, Posters, Presentations, Documentation...
  ☆18Updated last year
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆30Updated last year
• B-Lang-org / bdw
  BSC Development Workstation (BDW)
  ☆28Updated 4 months ago
• Twine-Umich / Twine
  ☆10Updated 2 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated this week
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆64Updated 4 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆57Updated 3 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆30Updated 3 weeks ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated 2 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆38Updated 2 months ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆33Updated 3 weeks ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 2 years ago
• masc-ucsc / fluid
  Fluid Pipelines
  ☆11Updated 6 years ago