CTSRD-CHERI / Flute
RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
☆11Updated 11 months ago
Alternatives and similar repositories for Flute:
Users that are interested in Flute are comparing it to the libraries listed below
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆29Updated this week
- RISC-V BSV Specification☆20Updated 5 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago
- RTLCheck☆20Updated 6 years ago
- CHERI-RISC-V model written in Sail☆58Updated last week
- Languages, Tools, and Techniques for Accelerator Design☆32Updated 3 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆13Updated 2 years ago
- ☆26Updated 7 years ago
- ☆13Updated 4 years ago
- A time-predictable processor for mixed-criticality systems☆58Updated 4 months ago
- A formalization of the RVWMO (RISC-V) memory model☆32Updated 2 years ago
- ☆10Updated 3 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- ☆19Updated 10 years ago
- A Hardware Pipeline Description Language☆43Updated last year
- BSC Development Workstation (BDW)☆28Updated 5 months ago
- A Rocket-based RISC-V superscalar in-order core☆31Updated this week
- A place to share libraries and utilities that don't belong in the core bsc repo☆35Updated 2 weeks ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- An instruction set simulator based on DBT-RISE implementing the RISC-V ISA☆35Updated 5 months ago
- Polyhedral High-Level Synthesis in MLIR☆30Updated 2 years ago
- Testing processors with Random Instruction Generation☆35Updated 3 weeks ago
- ☆15Updated 2 years ago
- An executable specification of the RISCV ISA in L3.☆41Updated 6 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated last year
- ☆24Updated 4 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆26Updated 2 months ago