Designs, infrastructure, and experiments around Race Logic
☆25Jun 25, 2020Updated 5 years ago
Alternatives and similar repositories for RaceLogic
Users that are interested in RaceLogic are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RSFQ cell library☆45Mar 21, 2023Updated 3 years ago
- Fork of main gem5 repo: https://gem5.googlesource.com/public/gem5/☆24Feb 20, 2026Updated last month
- A place to share libraries and utilities that don't belong in the core bsc repo☆38Feb 16, 2026Updated last month
- Verilog development and verification project for HOL4☆28Apr 25, 2025Updated 10 months ago
- ☆20Jan 31, 2026Updated last month
- A Language for Closed-form High-level ARchitecture Modeling☆21Feb 10, 2020Updated 6 years ago
- RISC-V port to Parallella Board☆13Aug 22, 2016Updated 9 years ago
- Source code of the processing-in-memory simulator used in the GRIM-Filter paper published at BMC Genomics in 2018: "GRIM-Filter: Fast See…☆11Feb 5, 2018Updated 8 years ago
- DUTH RISC-V Microprocessor☆25Dec 4, 2024Updated last year
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆297Mar 13, 2026Updated last week
- FPGA-based HyperLogLog Accelerator☆12Jul 13, 2020Updated 5 years ago
- Coderefinery project website.☆11Feb 27, 2026Updated 3 weeks ago
- Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors…☆16Jan 7, 2022Updated 4 years ago
- ☆11May 30, 2024Updated last year
- original 8bit CPU of ICF3-Z☆12Feb 20, 2020Updated 6 years ago
- Optimized Circuit Generation for Secure Multiparty Computation☆12Nov 25, 2019Updated 6 years ago
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆19Sep 26, 2024Updated last year
- ☆17Aug 7, 2023Updated 2 years ago
- A Toy-Purpose TPU Simulator☆22Jun 7, 2024Updated last year
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆47Jul 31, 2025Updated 7 months ago
- Low Precision Arithmetic Simulation in PyTorch - extension for posit and beyond☆16Dec 9, 2025Updated 3 months ago
- GenStore is the first in-storage processing system designed for genome sequence analysis that greatly reduces both data movement and comp…☆14Apr 6, 2022Updated 3 years ago
- Stochastic Computing for Deep Neural Networks☆33Nov 25, 2020Updated 5 years ago
- oneAPI Deep Neural Network Library (oneDNN)☆10Feb 2, 2022Updated 4 years ago
- Notionに毎日新しいarXiv論文のアブストラクト日本語訳 + αを表示するスクリプト☆13Jan 22, 2023Updated 3 years ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆446Mar 6, 2026Updated 2 weeks ago
- GuidedSampler: Coverage-guided Sampling of SMT Solutions☆15Jul 9, 2025Updated 8 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Nov 9, 2014Updated 11 years ago
- ☆12Jun 1, 2023Updated 2 years ago
- ☆17Jan 6, 2024Updated 2 years ago
- HyGen: Compact and Efficient Genome Sketching using Hyperdimensional Vectors☆30Aug 26, 2024Updated last year
- Optimization results for superconducting electronic (SCE) circuits☆18Dec 5, 2023Updated 2 years ago
- ☆10Aug 22, 2023Updated 2 years ago
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆37Oct 23, 2019Updated 6 years ago
- Haskell binding for Menoh DNN inference library☆12Nov 30, 2018Updated 7 years ago
- gem5 Tips & Tricks☆70Feb 25, 2020Updated 6 years ago
- RISC-V GPGPU☆36Mar 6, 2020Updated 6 years ago
- This repository contains sample code integrating Renode with Verilator☆26May 27, 2025Updated 9 months ago