Alternatives and similar repositories for RaceLogic

Users that are interested in RaceLogic are comparing it to the libraries listed below

• UCSBarchlab / Charm
  A Language for Closed-form High-level ARchitecture Modeling
  ☆21Updated 5 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆32Updated 2 years ago
• ymherklotz / vericert
  A formally verified high-level synthesis tool based on CompCert and written in Coq.
  ☆96Updated 2 weeks ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆118Updated last week
• SFU-HiAccel / pasta
  [FCCM 2023] PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs
  ☆12Updated 6 months ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆147Updated 2 months ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆67Updated 8 years ago
• falconcomputing / merlin-compiler
  Falcon Merlin Compiler
  ☆41Updated 5 years ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆40Updated 3 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 8 months ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆121Updated last week
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 11 years ago
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 4 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆81Updated last year
• Xilinx / merlin-compiler
  ☆60Updated 2 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 5 months ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• iwls2020-lsml-contest / iwls2020-lsml-contest
  ☆21Updated 3 years ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆75Updated 6 years ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆42Updated last week
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆45Updated 9 months ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆53Updated 2 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆30Updated 3 years ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆154Updated last year
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago