yonseicasl / NeuroSpectorLinks
NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
☆21Updated 9 months ago
Alternatives and similar repositories for NeuroSpector
Users that are interested in NeuroSpector are comparing it to the libraries listed below
Sorting:
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- ☆32Updated last year
- ☆24Updated 5 years ago
- ☆25Updated last year
- NeuraChip Accelerator Simulator☆15Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- Processing in Memory Emulation☆22Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- STONNE Simulator integrated into SST Simulator☆22Updated last year
- ☆42Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- ☆12Updated 2 years ago
- ☆10Updated 2 years ago
- ☆29Updated 4 years ago
- A general framework for optimizing DNN dataflow on systolic array☆38Updated 5 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 4 years ago
- ☆22Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- HW accelerator mapping optimization framework for in-memory computing☆25Updated 6 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- ☆36Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 10 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆67Updated this week
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 7 years ago
- ☆41Updated 9 months ago
- ☆19Updated 3 years ago