yonseicasl / NeuroSpector
NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
☆20Updated last week
Alternatives and similar repositories for NeuroSpector:
Users that are interested in NeuroSpector are comparing it to the libraries listed below
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆11Updated 7 months ago
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- ☆25Updated 11 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆35Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- NeuraChip Accelerator Simulator☆11Updated 11 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆48Updated 3 months ago
- ☆29Updated 6 months ago
- A Toy-Purpose TPU Simulator☆15Updated 9 months ago
- CGRA framework with vectorization support.☆29Updated this week
- Heterogenous ML accelerator☆18Updated 5 months ago
- ☆9Updated 2 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated 11 months ago
- ☆23Updated 4 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆20Updated 4 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆89Updated 6 months ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆31Updated 2 months ago
- An end-to-end GCN inference accelerator written in HLS☆19Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆27Updated 6 years ago
- ☆16Updated 2 years ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆11Updated 2 months ago