yonseicasl / NeuroSpectorLinks
NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
☆21Updated 6 months ago
Alternatives and similar repositories for NeuroSpector
Users that are interested in NeuroSpector are comparing it to the libraries listed below
Sorting:
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- NeuraChip Accelerator Simulator☆14Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- STONNE Simulator integrated into SST Simulator☆21Updated last year
- ☆31Updated 10 months ago
- ☆24Updated 4 years ago
- ☆35Updated 5 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- ☆25Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- Heterogenous ML accelerator☆19Updated 4 months ago
- ☆10Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆52Updated 8 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆22Updated 7 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- ☆13Updated 2 years ago
- Processing in Memory Emulation☆21Updated 2 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆56Updated 4 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 6 years ago
- HW accelerator mapping optimization framework for in-memory computing☆25Updated 3 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆68Updated 5 months ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆12Updated last year
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 8 years ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆12Updated last year
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆63Updated 9 months ago