Alternatives and similar repositories for NeuroSpector

Users that are interested in NeuroSpector are comparing it to the libraries listed below

• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆66Updated 4 years ago
• NeuraChip / neurachip
  NeuraChip Accelerator Simulator
  ☆14Updated last year
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• stonne-simulator / sst-elements-with-stonne
  STONNE Simulator integrated into SST Simulator
  ☆21Updated last year
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• hngenc / stellar
  ☆31Updated 11 months ago
• UCLA-VAST / hbmbench
  ☆24Updated 4 years ago
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• scalesim-project / krittika
  Heterogenous ML accelerator
  ☆19Updated 5 months ago
• he-actlab / planaria.code
  ☆29Updated 3 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆84Updated last year
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆30Updated 2 years ago
• hplp / PiMulator
  Processing in Memory Emulation
  ☆22Updated 2 years ago
• suchandler96 / gem5-NVDLA
  ☆35Updated 6 months ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆29Updated 2 years ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆64Updated 10 months ago
• CGCL-codes / ScalaBFS
  A Scalable BFS Accelerator on FPGA-HBM Platform
  ☆15Updated last year
• jasonlin316 / GCN-Inference-Acceleration-HLS
  An end-to-end GCN inference accelerator written in HLS
  ☆18Updated 3 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆64Updated 2 weeks ago
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆42Updated 8 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆81Updated 6 years ago
• tsinghua-ideal / spada-sim
  The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow
  ☆38Updated 2 years ago
• linghaosong / Serpens
  An HBM FPGA based SpMV Accelerator
  ☆15Updated last year
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆38Updated 4 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆70Updated last year
• Sibylau / HLS_designs
  Systolic array implementations for Cholesky, LU, and QR decomposition
  ☆46Updated 10 months ago
• pgroupATusc / GraphACT
  Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".
  ☆10Updated 5 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 3 years ago