Alternatives and similar repositories for optimus-hypervisor

Users that are interested in optimus-hypervisor are comparing it to the libraries listed below

• CMU-SAFARI / MemBen
  Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …
  ☆22Updated 4 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 3 years ago
• parsa-epfl / qflex
  Quick & Flexible Rack-Scale Computer Architecture Simulator
  ☆38Updated 2 months ago
• efeslab / lapidary
  Creating beautiful gem5 simulations
  ☆49Updated 4 years ago
• SwarmArch / sim
  ordspecsim: The Swarm architecture simulator
  ☆24Updated 2 years ago
• Krishnaps / Gem5-PCI-Express
  Gem5 with PCI Express integrated.
  ☆17Updated 6 years ago
• stanford-mast / zsim
  A fast and scalable x86-64 multicore simulator
  ☆31Updated 4 years ago
• jimstevens2001 / HybridSim
  Simulator of a memory controller to connect DRAMSim and FlashDIMMSim into one unified memory
  ☆17Updated last year
• pcie-bench / pcie-model
  ☆62Updated 3 months ago
• OCT-FPGA / OCT-Tutorials
  ☆30Updated 7 months ago
• gr-rahimi / APSim
  ☆23Updated 3 years ago
• barabanshek / Dagger
  HW/SW co-designed end-host RPC stack
  ☆20Updated 3 years ago
• darchr / gem5art
  Artifact, reproducibility, and testing utilites for gem5
  ☆21Updated 3 years ago
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆42Updated 7 years ago
• WukLab / Clio
  Clio, ASPLOS'22.
  ☆76Updated 3 years ago
• mariobadr / synfull-isca
  Synthetic Traffic Models Capturing a Full Range of Cache Coherent Behaviour
  ☆14Updated 6 years ago
• maltanar / fpga-booleanring-bfs
  Hybrid BFS on Xilinx Zynq
  ☆18Updated 9 years ago
• sstsimulator / sst-tutorials
  Tutorial Material from the SST Team
  ☆19Updated last year
• dskarlatos / ElasticCuckooHashing
  (elastic) cuckoo hashing
  ☆14Updated 4 years ago
• minmit / tonic
  A Programmable Hardware Architecture for Network Transport Logic
  ☆35Updated 3 years ago
• estwings57 / CasHMC
  CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube
  ☆21Updated 6 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• UCLA-VAST / hbmbench
  ☆23Updated 4 years ago
• bsc-mem / Mess-simulator
  A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.
  ☆24Updated last week
• fpgasystems / hacc
  ETHZ Heterogeneous Accelerated Compute Cluster.
  ☆33Updated last month
• dovedevic / blimp
  A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.
  ☆18Updated 3 years ago
• acsl-technion / nica
  An infrastructure for inline acceleration of network applications
  ☆30Updated 3 years ago
• stonne-simulator / sst-elements-with-stonne
  STONNE Simulator integrated into SST Simulator
  ☆19Updated last year
• programmable-scheduling / pifo-hardware
  ☆32Updated 9 years ago
• OSU-STARLAB / GPGPU-Ramulator-Simulator
  Replace original DRAM model in GPGPU-sim with Ramulator DRAM model
  ☆18Updated 6 years ago